Semiconductor structure having dielectric structure extending into second cavity of semiconductor fin

A semiconductor structure comprising:

• a first semiconductor fin and a second semiconductor fin on a substrate, the first semiconductor fin having a first longitudinal axis and the second semiconductor fin having a second longitudinal axis, wherein the first longitudinal axis and the second longitudinal axis are collinear;
• a third semiconductor fin parallel to the first semiconductor fin;
• isolation regions along opposing sides of the first semiconductor fin and the second semiconductor fin, the isolation regions extending between the first semiconductor fin and the third semiconductor fin;
• a first source/drain region in the first semiconductor fin;
• a second source/drain region in the second semiconductor fin;
• and
• an isolation structure between the first semiconductor fin and the second semiconductor fin, the isolation structure comprising:
• a first dielectric liner extending along a first sidewall of the first semiconductor fin and a second sidewall of the second semiconductor fin;
• and
• a dielectric fill on a first sidewall of the first dielectric liner and on a second sidewall of the first semiconductor fin, the first dielectric liner further being on a surface of the first semiconductor fin between the first sidewall of the first semiconductor fin and the second sidewall of the first semiconductor fin, wherein the dielectric fill extends lower than the first dielectric liner, wherein the first dielectric liner extends at least to a lower surface of the first source/drain region.

A semiconductor structure comprising:

• a first semiconductor fin and a second semiconductor fin on a substrate, a longitudinal axis of the first semiconductor fin being parallel to a longitudinal axis of the second semiconductor fin;
• a first gate structure over the first semiconductor fin;
• isolation regions adjacent the first semiconductor fin and the second semiconductor fin;
• a first source/drain region in the first semiconductor fin adjacent the first gate structure;
• a gate-cut structure adjacent the first gate structure, wherein a longitudinal axis of the gate-cut structure is parallel with the longitudinal axis of the first semiconductor fin;
• and
• an isolation structure adjacent the gate-cut structure, a longitudinal axis of the isolation structure intersecting the longitudinal axis of the second semiconductor fin, the isolation structure comprising:
• a first dielectric liner extending along a first portion of a sidewall of the second semiconductor fin, wherein the first dielectric liner directly contacts an upper surface of the isolation regions;
• and
• a dielectric fill on a second portion of the sidewall of the second semiconductor fin, wherein the first dielectric liner is between the first gate structure and the dielectric fill.