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US 12,684,757 B2Granted
Multi-layer random access memory and methods of manufacture
AssigneeTC Lab, Inc.
InventorHarry Luan
Life of this patent
Estimating the term…
Abstract
A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.
Claims6
A multi-layer thyristor memory array structure comprising:
- a semiconductor substrate;
- a plurality of layers of thyristors on the semiconductor substrate, the thyristors in each of the plurality of layers arrayed in rows by columns;
- a plurality of strings, each string including one thyristor from each of the layers so that the strings are arrayed in rows by columns;
- a plurality of first electrical connections arrayed in rows by columns, each first electrical connection corresponding to a string and connecting together a first terminal of each thyristor of the corresponding string;
- a first set of word line connections extending in parallel, each word line connection connecting rows of the first electrical connections together;
- and
- a first set of bit line connections extending in parallel on each layer, each bit line connection connecting together columns of thyristors on each layer, the first set of bit line connections on each layer extending outward on each layer away from the array further than the first set of bit line connections on the layer immediately above it.
4 more elements
A multi-layer random access memory array structure comprising:
- a semiconductor substrate;
- a plurality of layers on the semiconductor substrate, each of the layers including an x by y array of thyristor memory cells electrically isolated from each other;
- the array of thyristor memory cells in each layer aligned with the arrays of thyristor memory cells in other layers so that a thyristor memory cell in a layer is aligned with a thyristor memory cell in a layer above and with a thyristor memory cell in a layer below to form a string of thyristor memory cells, the string including one memory cell from each of the layers in the array;
- a plurality of first electrical connections extending through the layers, each first electrical connection corresponding to one string and connected to a first terminal of each thyristor memory cell in a string of thyristor memory cells;
- and
- a plurality of second electrical connections extending parallel to the layers, each second electrical connection in each layer connected to a second terminal of a plurality of thyristor memory cell in that layer of memory cells.
3 more elements
Dependencies are inferred from the claim text.