Deadlock detection and removal for mesh network for a processor-based system

A mesh network, comprising:

• a plurality of nodes configured to form the mesh network, each node comprising:
• a plurality of input pipeline circuits;
• a plurality of output storage pipeline circuits;
• and
• a plurality of arbiter circuits each configured to arbitrate data traffic by selectively linking a input pipeline circuit of the plurality of input pipeline circuits to an output pipeline circuit of the plurality of output pipeline circuits;
• and
• a stall detection circuit, comprising:
• a stall input coupled to an upstream stall output of an upstream node in the plurality of nodes, the stall input corresponding to the input pipeline circuit of the plurality of input pipeline circuits;
• and
• a stall output coupled to a downstream stall input of a downstream node in the plurality of nodes, the stall output corresponding to the output pipeline circuit of the plurality of output pipeline circuits;
• wherein the stall detection circuit is configured to assert the stall output when:
• the input pipeline circuit of the input pipeline circuits corresponding to the stall input is stalled,
• the output pipeline circuit of the output pipeline circuits corresponding to the stall output is stalled, and
• the arbiter circuits have linked the input pipeline circuit of the input pipeline circuits to the output pipeline circuit of the output pipeline circuits;
• and wherein the stall detection circuit is further configured to detect a deadlock in a cyclical dependency between a set of the plurality of nodes that includes a node of the plurality of nodes in which the stall detection circuit is provided, in response to both:
• the stall input indicating that the upstream stall output indicates that the upstream node is stalled, and
• the stall output being asserted indicating that the node is stalled.