Physically unclonable function (PUF) generation
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShih-Lien Linus Lu, Jui-Che Tsai, Cheng-En Lee
Life of this patent
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Abstract
A PUF generator includes a difference generator circuit with first and second transistors having a first predetermined VT. The difference generator circuit is configured to provide a first output signal for generating a PUF signature based on respective turn on times of the first and second transistors. An amplifier includes a plurality of transistors having a second predetermined VT. The amplifier is configured to receive the first output signal and output the PUF signature.
Claims20
A physically unclonable function (PUF) generator, comprising:
- a plurality of first transistors each connected to a power supply voltage and each having a first predetermined threshold voltage (VT);
- a plurality of second transistors each connected to the power supply voltage and each having the first predetermined VT, wherein each of the plurality of first transistors is connected to a first bit line and each of the plurality of second transistors is connected to a second bit line;
- and
- an amplifier including a plurality of third transistors each having a second predetermined VT that is different than the first predetermined VT and having a first input connected to the first bit line and a second input connected to the second bit line and configured to output a PUF signature based on differences in turn on times of the plurality of first transistors and the plurality of second transistors.
A physically unclonable function (PUF) generator, comprising:
- a first transistor that is connected to a power supply voltage and a first output, the first transistor having a first predetermined threshold voltage (VT);
- a second transistor that is connected to the power supply voltage and a second output, the second transistor having the first predetermined VT;
- and
- an amplifier including a plurality of transistors each having a second predetermined VT that is different than the first predetermined VT, the plurality of transistors providing a first inverter having a first inverter input connected to the second output and a first inverter output connected to the first output and a second inverter having a second inverter input connected to the first output and a second inverter output connected to the second output for generating a PUF signature based on differences in turn on times of the first transistor and the second transistor.
A circuit, comprising:
- a first inverter having a first output and including a first PMOS transistor having a first predetermined voltage threshold (VT) and connected to a first NMOS transistor having a second predetermined VT that is different than the first predetermined VT;
- a second inverter having a second output and including a second PMOS transistor having the first predetermined VT and connected to a second NMOS transistor having the second predetermined VT;
- and
- a discharge circuit including a third NMOS transistor configured to selectively connect the first output to a reference voltage and a fourth NMOS transistor configured to selectively connect the second output to the reference voltage,
- wherein the first inverter and the second inverter are cross-coupled inverters that generate a physically unclonable function (PUF) bit based on differences in turn on times of the first inverter and the second inverter.
Dependencies are inferred from the claim text.