Driver circuit

A differential driver circuit configured for use in a digital to analog conversion (DAC) cell, wherein:

• the differential driver circuit comprises a first single-ended driver circuit and a second single-ended driver circuit;
• the first single-ended driver circuit is configured to receive a data signal;
• the second single-ended driver circuit is configured to receive an inverse of the data signal;
• and
• each of the first and second single-ended driver circuits comprises the following:
• a positive single-edge latch configured to receive the data signal or the inverse and to provide a positive edge latched data signal based on the received data signal or inverse, said latch comprising a high side drive transistor controlled by an output signal provided between a first high side transistor switch and a series connection of a first low side transistor switch and a second low side transistor switch, wherein:
• the first high side transistor switch and the second low side transistor switch are configured to be controlled by the data signal or the inverse, and the first low side transistor switch is configured to be controlled by a first clock signal;
• the first high side transistor switch is configured to be activated by a low state of the data signal or the inverse;
• the second low side transistor switch is configured to be activated by a high state of the data signal or the inverse;
• and
• the first low side transistor switch is configured to be activated by a high state of the first clock signal,
• wherein the high side drive transistor is arranged to provide the positive edge latched data signal at an open drain terminal of the high side drive transistor;
• and
• a negative single-edge latch configured to receive the data signal or the inverse and to provide a negative edge latched data signal based on the received data signal or inverse, said latch comprising a low side drive transistor controlled by a negative output signal provided between a further first low side transistor switch and a series connection of a further first high side transistor switch and a further second high side transistor switch, wherein:
• the further first high side transistor switch and the further first low side transistor switch are configured to be controlled by the data signal or the inverse, and the further second high side transistor switch is configured to be controlled by a second clock signal;
• the further first high side transistor switch is configured to be activated by a low state of the data signal or the inverse;
• the further first low side transistor switch is configured to be activated by a high state of the data signal or the inverse;
• and
• the further second high side transistor switch is configured to be activated by a low state of the second clock signal,
• wherein the low side drive transistor is arranged to provide the negative edge latched data signal at an open drain terminal of the low side drive transistor;
• wherein the drain terminals of said high side drive transistor and said low side drive transistor are interconnected.