A Charge-Steering-Sampling Phase Discriminator (CSS-PD), with two input signals (Vref1) and (Vref2) and an output signal (Dout), input signals (Vref1) and (Vref2) being a pair of sinusoidal differential signals, the CSS-PD comprises:
- a Frac-N C-DAC, comprising a capacitors array (Cfrac) and a first two-way switches array correspondingly;
- a up-plate defined by a connection formed of ends of one half of capacitors of the capacitors array (Cfrac), a baseplate defined by another connection formed of ends of the other half of capacitors of the capacitors array (Cfrac), and the other ends of all capacitors of the capacitors array (Cfrac) connected with one corresponding first two-way switch respectively in order to receive a reference voltage (Vref,adc) or receive a low-level voltage (VSS);
- the first two-way switches array under control of timing-control signals (clk_frac);
- a CSS, comprising two first switches (S1) under the control of timing-control signals (clk_div) about a fractional frequency, two second switches (S2) under the control of timing-control signals (clk_css) about a trigger sampling pulse, and two transistors (M1) and (M2);
- timing-control signals (clk_css) activated when the falling edge of timing-control signals (clk_div) arrived;
- the two bases of transistors (M1) and (M2) receiving input signals (Vref1) and (Vref2) respectively;
- the two emitters of transistors (M1) and (M2) both receiving low-level voltage (VSS);
- the collector of transistor (M1) in turn connected with one first switch (S1) and one second switch (S2) in order to receive a high-level voltage VDD), and the collector of transistor (M2) in turn connected with another first switch (S1) and another second switch (S2) in order to receive high-level voltage (VDD);
- a SAR-ADC, comprising a capacitors array (Csar) and a second two-way switches array correspondingly;
- another up-plate defined by a connection formed of ends of one half of capacitors of the capacitors array (Csar), another baseplate defined by another connection formed of ends of the other half of capacitors of the capacitors array (Csar), and the other ends of all capacitors of the capacitors array (Csar) connected with one corresponding second two-way switch respectively in order to receive reference voltage (Vref,adc) or receive low-level voltage (VSS);
- the second two-way switches array under control of timing-control signals (clk_sar);
- the Frac-N C-DAC reset when the rising edge of the timing-control signal (clk_sar) arrived;
- the two up-plates both connected with the collector of transistor (M1), and the two baseplates both connected with the collector of transistor (M2);
- wherein output signal (Dout) is defined by the output signal (Nfrac) between the up-plate and the baseplate of the SAR-ADC;
- signal (Dfrac) is defined by the output signal between the up-plate and the baseplate of the Frac-N C-DAC, then is also the input signal (Nint) of the SAR-ADC;
- the CSS-PD has a controlling method comprising:
- (1) charge presetting
- when timing-control signals (clk_div) was on the high level voltage, the two up-plates were charged to high-level voltage (VDD) by switching on S1 under the control of timing-control signals (clk_div), and the two baseplates were set on low-level voltage (VSS) by switching on the two two-way switches arrays under the control of timing-control signals (clk_frac) and timing-control signals (clk_sar) respectively;
- (2) charge-steering sampling
- when the falling edge of timing-control signals (clk_div) was arrived and timing-control signals (clk_css) was activated, a phase difference (ΔVerr,pn) defined by the phase difference between timing-control signals (clk_div) and the two input signals (Vref1) and (Vref2) was detected by switching on the second switch (S2) under the control of timing-control signals (clk_css);
- (3) fractional charge compensating
- when phase difference (ΔVerr,pn) included two errors (ΔVerr,pn) and ΔVerr,frac, error (ΔVerr,pn) defined by PN and error (ΔVerr,frac) defined by a periodic error between the two adjacent periods of input signals (Vref1) and (Vref2), error (ΔVerr,frac) had fractional charge compensating by setting part of the capacitors of the capacitors array (Cfrac) to reference voltage (Vref,adc) because that part of two-way switches of the first two-way switches array were switched on respectively under the control of timing-control signals (clk_frac);
- reference voltage (Vref,adc) was satisfied the following formula:
- ΔVerr,frac=Dfrac·Cunit/(Cfrac+Csar)·Vref,adc;
- in the formula, Cunit is for capacitance of capacitors array (Cfrac), Cfrac is also for capacitance of capacitors array (Cfrac), Csar is also for capacitance of capacitors array (Csar);
- (4) digitalizing
- phase difference (ΔVerr,pn) was digitalized by the SAR-ADC, and the output signal (Dout) was output accordingly.