Hybrid scan chains with flip-flops and latches
AssigneeSambaNova Systems, Inc.
InventorsThomas Ziaja, Paul Jordan
Life of this patent
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AssigneeSambaNova Systems, Inc.
InventorsThomas Ziaja, Paul Jordan
Estimating the term…
An electronic circuit features a hybrid scan chain design comprising a flip-flop-based part of the scan chain and a latch-based part of the scan chain. The latch-based part may be included in an array of memory cells and includes one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The circuit includes a memory element interfacing the scan out (SO) output of the flip-flop-based scan chain with the scan in (SI) input of the latch-based scan chain. The memory element captures and retains the value of the final flip-flop in the flip-flop-based scan chain, enabling subsequent access by the initial latch in the latch-based scan chain without loss of data.
An electronic circuit comprising a flip-flop-based scan chain coupled with a latch-based scan chain, the electronic circuit further comprising:
A method to interface between a last flip-flop in a flip-flop-based part of a scan chain with a first latch in a latch-based part of the scan chain, wherein the latch-based scan chain comprises a chain of scannable latches, the method comprising:
A method to interface between a last flip-flop in a flip-flop-based part of a scan chain with a first latch in a latch-based part of the scan chain, wherein the latch-based scan chain comprises a chain of scannable latches and the first latch in the latch-based part of the scan chain is not data carrying in a functional mode, the method comprising:
Dependencies are inferred from the claim text.