Scannable memory subsystem

A semiconductor memory subsystem, comprising:

• an array of memory cells including a scan chain having a first chain segment that includes N memory cells of the array of memory cells, wherein N is an integer number greater than 1;
• and
• a sequence generator having a scan clock input (a SCLK input) and at least N−1 scan sub-clock outputs, wherein the at least N−1 scan sub-clock outputs are respectively coupled to one of the N memory cells in the first chain segment, and wherein the sequence generator, in response to receiving a pulse in a signal on the SCLK input (an SCLK signal), generates a sequence of non-overlapping pulses that are sent to the at least N−1 scan sub-clock outputs with a single pulse of the sequence of non-overlapping pulses on each of the at least N−1 scan sub-clock outputs;
• and
• wherein a total duration of the sequence of non-overlapping pulses is equal to or less than a total duration of a cycle of the SCLK signal.