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US 12,682,958 B2Granted
Memory device and method of erasure operations using GIDL and negative wordline voltages
AssigneeSK hynix Inc.
InventorChang Beom Woo
Life of this patent
Estimating the term…
Abstract
A memory device and a method of operating the same are provided. The memory device may include a memory block including a plurality of memory cells, peripheral circuits configured to perform an erase operation including a gate induced drain leakage (GIDL) current generation operation and a data erase operation using an GIDL current on the memory block, and control logic configured to control the peripheral circuits to perform the erase operation, wherein the control logic is configured to control the peripheral circuits to apply a negative voltage to word lines of the memory block during the GIDL current generation operation.
Claims19
A memory device comprising:
- a memory block including a plurality of memory cells;
- peripheral circuits configured to perform an erase operation including a gate induced drain leakage (GIDL) current generation operation and a data erase operation using a GIDL current on the memory block;
- and
- control logic configured to control the peripheral circuits to perform the erase operation;
- wherein the control logic is configured to control the peripheral circuits to apply a negative voltage to word lines of the memory block during the GIDL current generation operation, and
- wherein the peripheral circuits comprise:
- a voltage generating circuit configured to generate a first erase voltage, apply the first erase voltage to a source line of the memory block, and generate the negative voltage during the GIDL current generation operation;
- and
- a row decoder configured to apply the negative voltage generated by the voltage generating circuit to the word lines during the GIDL current generation operation and to apply a ground voltage to the word lines during the data erase operation.
6 more elements
A memory device comprising:
- a memory block including a plurality of memory cells;
- a voltage generating circuit comprising a negative voltage generator, wherein the voltage generating circuit is configured to generate a first erase voltage and apply the first erase voltage to a source line of the memory block during a GIDL current generation operation of an erase operation, and to generate a second erase voltage and apply the second erase voltage to the source line during a data erase operation of the erase operation;
- a row decoder configured to apply an operating voltage to word lines of the memory block;
- and
- an erase operation controller configured to control the voltage generating circuit and the row decoder during the erase operation,
- wherein the erase operation controller is configured to control the negative voltage generator to generate a negative voltage and control the row decoder to apply the negative voltage to the word lines during the GIDL current generation operation, and
- wherein the row decoder is configured to apply a ground voltage to a drain select line and a source select line of the memory block during the GIDL current generation operation, and to cause the drain select line and the source select line to float when the first erase voltage reaches a voltage threshold.
4 more elements
A method of operating a memory device, the method comprising:
- applying a first erase voltage to a source line or bit lines of a memory block during a first period;
- applying a negative voltage to word lines of the memory block during at least part of the first period;
- applying a second erase voltage to the source line or the bit lines during a second period following the first period;
- and
- applying a ground voltage to the word lines during the second period.
2 more elements
A method comprising:
- during a first period:
- applying a first erase voltage to a source line or bit lines of a memory block at least until the first erase voltage reaches a voltage threshold, wherein a gate induced drain leakage current is generated when the first erase voltage reaches the voltage threshold;
- causing a drain select line and a source select line to float when the first erase voltage reaches the voltage threshold;
- and
- applying a negative voltage to word lines of the memory block;
- and
- during a second period following the first period:
- applying a second erase voltage to the source line or the bit lines during;
- and applying a ground voltage to the word lines.
6 more elements
Dependencies are inferred from the claim text.