Memory structure including three-dimensional nor memory strings and method of fabrication

A three-dimensional memory structure formed above a planar surface of a semiconductor substrate, the memory structure comprising:

• a plurality of thin-film storage transistors being organized as a plurality of stacks of NOR memory strings, the storage transistors within each NOR memory string sharing a common source layer and a common drain layer, spaced apart by a first isolation layer, with each layer extending along a first direction, the common source layer and the common drain layer each comprising a semiconductor layer of a first conductivity type and a conductive layer, the conductive layer being formed between the first isolation layer and the respective semiconductor layer and comprising a metallic conductive material;
• wherein:
• (i) each NOR memory string extends along the first direction that is substantially parallel to the planar surface of the semiconductor substrate,
• (ii) the NOR memory strings of each stack are (a) provided one on top of another along a second direction substantially normal to the planar surface, and (b) isolated one from the other memory string by a second isolation layer;
• (iii) an additional semiconductor layer of a second conductivity is provided adjacent each stack of NOR memory strings and, with respect to each NOR memory string within the stack, in contact with the common source layer and the common drain layer of the NOR memory string, thus providing channel regions for the storage transistors of the NOR memory string;
• (iv) a gate dielectric layer is provided adjacent the additional semiconductor layer;
• and
• (v) a plurality of conductors are provided between adjacent stacks of NOR memory strings, each conductor extending along the second direction, and each serving as a common gate electrode for a group of storage transistors in the NOR memory strings of the adjacent stacks.