Apparatuses and methods for single and multi memory cell architectures
AssigneeMicron Technology, Inc.
InventorsYang Lu, Toby D. Robbs, Christopher J. Kawamura, Kang-Yong Kim
Life of this patent
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Abstract
Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.
Claims17
An apparatus comprising:
- a first region of a memory array having a 1T architecture;
- a second region of the memory array having a MT architecture;
- a plurality of local input-output (LIO) lines extending across the first region and the second region;
- and
- a third region disposed between the first region and the second region,
- wherein a first portion of the plurality of LIO lines extends through the first region in a lower portion of the memory array and extends from the lower portion to an upper portion of the memory array in the third region and extends through the second region in the upper portion, and
- wherein a second portion of the plurality of LIO lines extends through the first region in the upper portion of the memory array and extends from the upper portion to the lower portion in the third region and extends through the second region in the lower portion.
An apparatus comprising:
- a first region of a memory array;
- a second region of the memory array, wherein the first region comprises a MT architecture and the second region comprises the 1T architecture;
- a plurality of local input-output (LIO) lines extending across the first region and the second region;
- a third region disposed between the first region and the second region, wherein a portion of the LIO lines twist in the third region;
- a plurality of memory cells;
- a plurality of sense amplifiers in the first region;
- a plurality of bit lines coupled to the plurality of memory cells and the first plurality of sense amplifiers in the first region, wherein at least two of the plurality of memory cells are coupled to a sense amplifier of the plurality of sense amplifiers during a sense operation
- a fourth region on an opposite side of the first region from the third region;
- and
- a fifth region adjacent to the fourth region, wherein the fifth region has the 1T architecture, wherein the plurality of LIO lines extend across the fourth region and the fifth region from the first region, wherein the portion of the LIO lines twist in the fourth region.
Dependencies are inferred from the claim text.