US 12,682,941 B2Granted

Semiconductor device comprising 3D-memory

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsTomoaki Atsumi, Junpei Sugao

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Abstract

The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.

Claims12

Dependent claims

A semiconductor device comprising:

a plurality of first transistors;
a plurality of second transistors;
and
a plurality of first capacitors,
wherein a first transistor of the plurality of first transistors is provided over a second transistor of the plurality of first transistors,
wherein a first transistor of the plurality of second transistors is provided over a second transistor of the plurality of second transistors,
wherein a first insulator is provided over the second transistor of the plurality of first transistors,
wherein a first semiconductor is provided over the first insulator,
wherein the first semiconductor comprises a region configured to function as a channel formation region of the first transistor of the plurality of first transistors,
wherein a first conductor is provided over the first insulator and the first semiconductor,
wherein the first conductor comprises a first region configured to function as one of a source electrode and a drain electrode of the first transistor of the plurality of first transistors, a second region configured to function as a gate electrode of the first transistor of the plurality of second transistors, and a third region configured to function as a first electrode of one capacitor of the plurality of first capacitors,
wherein a second insulator is provided over the first conductor,
wherein a second conductor is provided over the second insulator,
wherein the second conductor comprises a region configured to function as a second electrode of the one capacitor of the plurality of first capacitors, and
wherein a second semiconductor comprises a first region configured to function as one of a source electrode and a drain electrode of the first transistor of the plurality of second transistors, a second region configured to function as a channel formation region of the first transistor of the plurality of second transistors, a third region configured to function as the other of the source electrode and the drain electrode of the first transistor of the plurality of second transistors, a fourth region configured to function as one of a source electrode and a drain electrode of the second transistor of the plurality of second transistors, and a fifth region configured to function as a channel formation region of the second transistor of the plurality of second transistors.

12 more elements

A semiconductor device comprising:

a plurality of first transistors;
a plurality of second transistors;
and
a plurality of first capacitors,
wherein a first transistor of the plurality of first transistors is provided over a second transistor of the plurality of first transistors,
wherein a first transistor of the plurality of second transistors is provided over a second transistor of the plurality of second transistors,
wherein a first insulator is provided over the second transistor of the plurality of first transistors,
wherein a first semiconductor is provided over the first insulator,
wherein the first semiconductor comprises a region configured to function as a channel formation region of the first transistor of the plurality of first transistors,
wherein a first conductor is provided over the first insulator and the first semiconductor,
wherein the first conductor comprises a first region configured to function as one of a source electrode and a drain electrode of the first transistor of the plurality of first transistors, a second region configured to function as a gate electrode of the first transistor of the plurality of second transistors, and a third region configured to function as a first electrode of one capacitor of the plurality of first capacitors,
wherein a second insulator is provided over the first conductor,
wherein a second conductor is provided over the second insulator,
wherein the second conductor comprises a region configured to function as a second electrode of the one capacitor of the plurality of first capacitors,
wherein a second semiconductor comprises a first region configured to function as one of a source electrode and a drain electrode of the first transistor of the plurality of second transistors, a second region configured to function as a channel formation region of the first transistor of the plurality of second transistors, a third region configured to function as the other of the source electrode and the drain electrode of the first transistor of the plurality of second transistors, a fourth region configured to function as one of a source electrode and a drain electrode of the second transistor of the plurality of second transistors, and a fifth region configured to function as a channel formation region of the second transistor of the plurality of second transistors, and
wherein the first semiconductor comprises an oxide semiconductor including indium.

13 more elements

A semiconductor device comprising:

a plurality of first transistors;
a plurality of second transistors;
and
a plurality of first capacitors,
wherein a first transistor of the plurality of first transistors is provided over a second transistor of the plurality of first transistors,
wherein a first transistor of the plurality of second transistors is provided over a second transistor of the plurality of second transistors,
wherein a first insulator is provided over the second transistor of the plurality of first transistors,
wherein a first semiconductor is provided over the first insulator,
wherein the first semiconductor comprises a region configured to function as a channel formation region of the first transistor of the plurality of first transistors,
wherein a first conductor is provided over the first insulator and the first semiconductor,
wherein the first conductor comprises a first region configured to function as one of a source electrode and a drain electrode of the first transistor of the plurality of first transistors, a second region configured to function as a gate electrode of the first transistor of the plurality of second transistors, and a third region configured to function as a first electrode of one capacitor of the plurality of first capacitors,
wherein a second insulator is provided over the first conductor,
wherein a second conductor is provided over the second insulator,
wherein the second conductor comprises a region configured to function as a second electrode of the one capacitor of the plurality of first capacitors,
wherein a second semiconductor comprises a first region configured to function as one of a source electrode and a drain electrode of the first transistor of the plurality of second transistors, a second region configured to function as a channel formation region of the first transistor of the plurality of second transistors, a third region configured to function as the other of the source electrode and the drain electrode of the first transistor of the plurality of second transistors, a fourth region configured to function as one of a source electrode and a drain electrode of the second transistor of the plurality of second transistors, and a fifth region configured to function as a channel formation region of the second transistor of the plurality of second transistors,
wherein the first semiconductor comprises an oxide semiconductor including indium,
wherein the second semiconductor comprises silicon,
wherein, in a cross-sectional view, the first semiconductor extends in a first direction parallel to a substrate over which the plurality of first transistors and the plurality of second transistors are formed, and
wherein, in the cross-sectional view, the second semiconductor extends in a second direction perpendicular to the substrate.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/646,415Filed 25 Apr 2024 · continuation
Priority: JP 2015-10676126 May 2015
Published: US 2024/0296881 A15 Sep 2024
Granted: 14 Jul 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

G11C 11/4094
Read-write [R-W] circuits: bit-line management or control circuits
G11C 11/401
Using transistors: forming cells needing refreshing or charge regeneration, i.e. dynamic cells
G11C 11/4096
Read-write [R-W] circuits: input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G11C 11/4097
Read-write [R-W] circuits: bit-line organisation, e.g. bit-line layout, folded bit lines

Family

Application15/164,133Parent of this continuation · filed 25 May 2016
Application16/103,157Parent of this continuation · filed 14 Aug 2018
US 10,056,131 B2Parent of this continuation · filed 21 Aug 2018
Application16/732,555Parent of this continuation · filed 2 Jan 2020
US 10,529,413 B2Parent of this continuation · filed 7 Jan 2020
Application17/826,707Parent of this continuation · filed 27 May 2022
US 11,355,179 B2Parent of this continuation · filed 7 Jun 2022
US 2024/0296881 A1Pre-grant publication · published 5 Sep 2024
US 11,972,790 B2Parent of this continuation
US 2016/0351572 A1Published application
US 2019/0074049 A1Published application
US 2020/0211627 A1Published application
US 2022/0293164 A1Published application
US 12,682,941 B2This patent

From the US filing history. Foreign family members aren’t listed.