Heusler alloy based spin-transfer-torque magnetic tunnel junctions for flash memory and the like

A method of operating a memory array, comprising:

• providing a memory array, the array comprising:
• a plurality of bit lines and a plurality of complementary bit lines forming a plurality of bit line-complementary bit line pairs;
• a plurality of word lines intersecting the plurality of bit line pairs at a plurality of cell locations;
• and
• a plurality of magnetic tunnel junction cells located at each of the plurality of cell locations, each of the magnetic tunnel junction cells being electrically connected to a corresponding bit line and selectively interconnected to a corresponding one of the complementary bit lines under control of a corresponding one of the word lines, each of the plurality of magnetic tunnel junction cells comprising:
• a substrate;
• a seed layer overlying the substrate;
• a nitride layer, overlying the seed layer;
• a templating layer, outward of the nitride layer, comprising a binary alloy having an alternating layer lattice structure, and having a thickness greater than 50 Angstroms;
• a magnetic layer overlying the templating layer, the magnetic layer comprising a Heusler compound and exhibiting perpendicular magnetic anisotropy (PMA);
• a tunnel barrier outward of the magnetic layer;
• and
• a magnetic layer outward of the tunnel barrier;
• providing peripheral circuitry coupled to the plurality of bit line-complementary bit line pairs and the plurality of word lines, a power supply, and a controller coupled to the power supply and the peripheral circuitry;
• applying signals, by way of the peripheral circuitry, the power supply, and the controller, cooperatively, to the word lines to cause a first subset of the cells to store first logical values, a second subset of the cells to store second logical values, and a third subset of the cells to store third logical values, the first, second, and third logical values being different;
• and
• reading the first, second, and third stored logical values via the bit lines and the complementary bit lines.

A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a memory array, wherein the (HDL design structure) comprises:

• a plurality of bit lines and a plurality of complementary bit lines forming a plurality of bit line-complementary bit line pairs;
• a plurality of word lines intersecting the plurality of bit line pairs at a plurality of cell locations;
• a plurality of magnetic tunnel junction cells located at each of the plurality of cell locations, each of the magnetic tunnel junction cells being electrically connected to a corresponding bit line and selectively interconnected to a corresponding one of the complementary bit lines under control of a corresponding one of the word lines, each of the plurality of magnetic tunnel junction cells comprising:
• a substrate;
• a seed layer overlying the substrate;
• a nitride layer, overlying the seed layer;
• a templating layer, outward of the nitride layer, comprising a binary alloy having an alternating layer lattice structure, and having a thickness greater than 50 Angstroms;
• a magnetic layer overlying the templating layer, the magnetic layer comprising a Heusler compound and exhibiting perpendicular magnetic anisotropy (PMA);
• a tunnel barrier outward of the magnetic layer;
• and
• a magnetic layer outward of the tunnel barrier;
• peripheral circuitry coupled to the plurality of bit line-complementary bit line pairs and the plurality of word lines;
• a power supply;
• and
• a controller coupled to the power supply and the peripheral circuitry,
• wherein the peripheral circuitry, the power supply, and the controller are cooperatively configured to:
• apply signals to the word lines to cause a first subset of the cells to store first logical values, a second subset of the cells to store second logical values, and a third subset of the cells to store third logical values, wherein the first, second, and third logical values are all different;
• and
• read the first, second, and third stored logical values via the bit lines and the complementary bit lines.