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US 12,682,936 B2Granted
Method for configuring multiple input-output channels
AssigneeMicron Technology, Inc.
InventorsDean E. Walker, Tony Brewer
Life of this patent
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Abstract
A method includes setting an order of input-output channels of a column of a first chiplet of multiple chiplets of a chiplet-based system, wherein one or more of the multiple chiplets include field-configurable input-output channels arranged at a periphery of the chiplets; and programming a second chiplet of the multiple chiplets to change an order of input-output channels of a column of the second chiplet to match the order of input-output channels of the column of the first chiplet.
Claims20
A chiplet system comprising:
- multiple chiplets including a host interface chiplet and one or more subordinate chiplets, wherein the host interface chiplet includes:
- multiple input-output (I/O) cells arranged into multiple I/O channels, and the multiple I/O channels are arranged into multiple columns, and the multiple columns are arranged at a periphery of the host interface chiplet, wherein the I/O channels of the columns are bondable together to form a channel interface including multiple combined channels;
- multiple channel configuration registers for the multiple I/O channels, wherein a channel configuration register includes a writeable bond field to indicate a number of channels to bond together into a wider combined channel interface;
- and
- a host interface to receive channel configuration data for the multiple channel configuration registers from a host device.
2 more elements
A memory controller chiplet, comprising:
- processing circuitry including one or more processors configured to perform memory operations received from a host device for a memory array;
- multiple input-output (I/O) cells arranged into multiple I/O channels, and the multiple I/O channels are arranged into multiple columns, and the multiple columns are arranged at a periphery of the host interface chiplet, wherein the I/O channels of the columns are bondable together to form a channel interface including multiple combined channels, and wherein the channels of the chiplet are combinable together into a channel that spans multiple columns;
- and
- multiple column capability registers for the multiple columns, wherein each column capability register includes a column reversal capable field writeable to indicate that the order of the I/O channels of a corresponding column are reversible.
1 more element
Dependencies are inferred from the claim text.