# US 12,682,852 B2 · Display substrate having gate driving circuit and display device

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- Number: US 12,682,852 B2
- Document ID: US12682852B2
- Status: Granted
- Kind: B2
- Application number: 18/019,987
- Filed: 2022-02-24
- Published: 2023-09-07
- Granted: 2026-07-14
- Earliest claimed: 2021-05-31
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: BOE Technology Group Co., Ltd.
- Inventors: Guangliang Shang; Libin Liu; Li Wang; Yu Feng; Baoyun Wu
- Web page: https://patentgrep.com/patent/US12682852B2

## CPC

- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/3674: {Details of drivers for scan electrodes}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- H10K 59/1213: {the pixel elements being TFTs}
- H10K 59/1216: {the pixel elements being capacitors}
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2310/0281: Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/061: for resetting or blanking
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A display substrate and a display device. The display substrate includes: a base substrate; and a gate driving circuit; the gate driving circuit includes a plurality of shift register circuits; each shift register circuit includes: an input circuit, a control circuit, an output circuit, and an output noise reduction circuit; the control circuit includes a first transistor, a second transistor, and a third transistor; the control circuit is connected to the first node, a second node and a third node; at least two selected from group consisting of an active layer of the first transistor, an active layer of the second transistor, and an active layer of the third transistor extend in a first direction and are arranged in the first direction.

## Claims

### Claim 1

A display substrate, comprising:
a base substrate; and
a gate driving circuit provided on a peripheral region of the base substrate, wherein the gate driving circuit comprises a plurality of shift register circuits that are arranged in a first direction,
each shift register circuit comprises an input circuit, a control circuit, an output circuit and an output noise reduction circuit,
the input circuit is connected to an input terminal and configured to control a level of a first node in response to an input signal that is input by the input terminal,
the control circuit is connected to the first node, a second node and a third node,
the output circuit is connected to the third node and an output terminal, respectively, and is configured to provide an output signal to the output terminal,
the output noise reduction circuit is connected to the second node and the output terminal, respectively, and is configured for noise reduction on the output terminal,
the control circuit comprises a first transistor, a second transistor and a third transistor,
a first electrode of the first transistor is directly connected to the second node and configured to control a level of the second node,
a first electrode of the second transistor is connected to the third node, a second electrode of the second transistor is connected to a first voltage line to receive a first voltage, a gate electrode of the second transistor is directly connected to the first node, and the second transistor is configured to control a level of the third node in response to the level of the first node,
a first electrode of the third transistor is connected to the third node and configured to control the level of the third node, and
at least two selected from group consisting of an active layer of the first transistor, an active layer of the second transistor and an active layer of the third transistor extend in the first direction and are sequentially arranged in the first direction,
wherein the control circuit further comprises: a fourth transistor and a fifth transistor,
a first electrode of the fourth transistor is connected to the first voltage line to receive the first voltage, a second electrode of the fourth transistor is connected to the second node, a gate electrode of the fourth transistor is connected to a first control node, and the fourth transistor is configured to control the level of the second node in response to a level of the first control node;
a first electrode of the fifth transistor is connected to the first voltage line to receive the first voltage, a second electrode of the fifth transistor is connected to the second node, a gate electrode of the fifth transistor is connected to a reset signal line, and the fifth transistor is configured to reset the second node; and
an active layer of the fourth transistor and an active layer of the fifth transistor extend in the first direction, respectively, and are arranged along a second direction, and the second direction intersects with the first direction.

### Claim 2 (depends on 1)

The display substrate according to claim 1, wherein the active layer of the first transistor, the active layer of the second transistor and the active layer of the third transistor extend in the first direction and are sequentially arranged in the first direction.

### Claim 3 (depends on 1)

The display substrate according to claim 1, wherein the active layer of the fifth transistor and the active layer of the second transistor are integrally provided.

### Claim 4 (depends on 3)

The display substrate according to claim 3, wherein in the first direction, the active layer of the fourth transistor and the active layer of the fifth transistor are located between the active layer of the first transistor and the active layer of the second transistor.

### Claim 5 (depends on 3)

The display substrate according to claim 3, wherein the control circuit further comprises: a sixth transistor and a seventh transistor, and the input circuit comprises an eighth transistor,
a gate electrode of the sixth transistor is connected to the first node, a first electrode of the sixth transistor is connected to a first clock signal line to receive a first clock signal, and a second electrode of the sixth transistor is connected to a fourth node;
a gate electrode of the seventh transistor is connected to a second clock signal line to receive a second clock signal, a first electrode of the seventh transistor is connected to a second voltage line to receive a second voltage, and a second electrode of the seventh transistor is connected to the fourth node; and
an active layer of the seventh transistor and an active layer of the eighth transistor are sequentially arranged in the first direction and extend along the first direction.

### Claim 6 (depends on 1)

The display substrate according to claim 1, wherein in the first direction, the active layer of the fourth transistor and the active layer of the fifth transistor are located between the active layer of the first transistor and the active layer of the second transistor.

### Claim 7 (depends on 1)

The display substrate according to claim 1, wherein the control circuit further comprises: a sixth transistor and a seventh transistor, and the input circuit comprises an eighth transistor,
a gate electrode of the sixth transistor is connected to the first node, a first electrode of the sixth transistor is connected to a first clock signal line to receive a first clock signal, and a second electrode of the sixth transistor is connected to a fourth node;
a gate electrode of the seventh transistor is connected to a second clock signal line to receive a second clock signal, a first electrode of the seventh transistor is connected to a second voltage line to receive a second voltage, and a second electrode of the seventh transistor is connected to the fourth node; and
an active layer of the seventh transistor and an active layer of the eighth transistor are sequentially arranged in the first direction and extend along the first direction.

### Claim 8 (depends on 7)

The display substrate according to claim 7, wherein an active layer of the sixth transistor is located on a side of the active layer of the seventh transistor and the active layer of the eighth transistor that is away from the first clock signal line, and the active layer of the sixth transistor extends along the first direction.

### Claim 9 (depends on 7)

The display substrate according to claim 7, wherein the control circuit further comprises a ninth transistor, a tenth transistor and a first capacitor,
a gate electrode of the ninth transistor is connected to the second voltage line, a first electrode of the ninth transistor is connected to the first node, and a second electrode of the ninth transistor is connected to a second control node;
a gate electrode of the tenth transistor is connected to the second control node, a first electrode of the tenth transistor is connected to a third clock signal line to receive a third clock signal, and a second electrode of the tenth transistor is connected to a first electrode of the first capacitor;
a second electrode of the first capacitor is connected to the second control node;
the second control node is connected to a gate electrode of the first transistor, and the gate electrode of the first transistor is connected to a second electrode of the first transistor; and
an active layer of the ninth transistor extends along the first direction and is sequentially arranged with the seventh transistor and the eighth transistor in the first direction, and an active layer of the tenth transistor extends along the second direction.

### Claim 10 (depends on 9)

The display substrate according to claim 9, wherein
an orthographic projection of the active layer of the ninth transistor on the base substrate, an orthographic projection of the active layer of the eighth transistor on the base substrate, and an orthographic projection of the active layer of the seventh transistor on the base substrate are located on a first side of an orthographic projection of the first capacitor on the base substrate, and are sequentially arranged along the first direction, an orthographic projection of the active layer of the first transistor on the base substrate is located on a second side of the first capacitor on the base substrate, the first side of the first capacitor on the base substrate is a side of the first capacitor that is close to the first clock signal line on the base substrate, the second side of the first capacitor on the base substrate is a side of the first capacitor that is away from the first clock signal line on the base substrate, and the orthographic projection of the first capacitor on the base substrate is located between the ninth transistor and the tenth transistor in the first direction; or
the first capacitor comprises an extension portion that is close to the first clock signal line, and in the first direction, an orthographic projection of the extension portion on the base substrate is located between an orthographic projection of the tenth transistor on the base substrate and an orthographic projection of the ninth transistor on the base substrate, and the first transistor is located on the side of the first capacitor that is away from the first clock signal line on the base substrate.

### Claim 11 (depends on 9)

The display substrate according to claim 9, wherein the tenth transistor is connected to the first electrode of the first capacitor through a first via hole and a second via hole, and an orthographic projection of the first via hole and an orthographic projection of the second via hole on the base substrate are within the orthographic projection of the first capacitor on the base substrate.

### Claim 12 (depends on 9)

The display substrate according to claim 9, wherein the control circuit further comprises an eleventh transistor, a twelfth transistor and a second capacitor,
a gate electrode of the eleventh transistor is connected to the second voltage line, a first electrode of the eleventh transistor is connected to the fourth node, and a second electrode of the eleventh transistor is connected to a third control node:
a gate electrode of the twelfth transistor is connected to the third control node, a first electrode of the twelfth transistor is connected to a fourth clock signal line to receive a fourth clock signal, and a second electrode of the twelfth transistor is connected to a first electrode of the second capacitor;
a second electrode of the second capacitor is connected to the first control node; and
an active layer of the eleventh transistor extends along the first direction and is sequentially arranged with the active layer of the sixth transistor in the first direction, and the active layer of the ninth transistor and the active layer of the eleventh transistor are sequentially arranged in the second direction.

### Claim 13 (depends on 12)

The display substrate according to claim 12, wherein
an active layer of the twelfth transistor extends along the second direction, and in the second direction, an orthographic projection of the active layer of the twelfth transistor on the base substrate and an orthographic projection of the second capacitor on the base substrate are located between an orthographic projection of the active layer of the sixth transistor on the base substrate and an orthographic projection of the active layer of the third transistor on the base substrate, the orthographic projection of the active layer of the twelfth transistor on the base substrate is located on a side of the orthographic projection of the second capacitor on the base substrate that is away from the first capacitor, and in the second direction, the active layer of the third transistor is located on a side of the twelfth transistor that is away from the second capacitor; or
the active layer of the twelfth transistor extends along the second direction, and the orthographic projection of the active layer of the twelfth transistor on the base substrate and the orthographic projection of the active layer of the sixth transistor on the base substrate are located on a side of the orthographic projection of the second capacitor on the base substrate that is close to the orthographic projection of the first capacitor on the base substrate.

### Claim 14 (depends on 9)

The display substrate according to claim 9, wherein a width-to-length ratio of a channel of the tenth transistor is greater than 1.75.

### Claim 15 (depends on 1)

The display substrate according to claim 1, wherein a width-to-length ratio of a channel of the first transistor is 3.

### Claim 16 (depends on 1)

The display substrate according to claim 1, wherein the active layer of the first transistor is connected to the first electrode of the first transistor through a third via hole, and an orthographic projection of a channel of the first transistor on the base substrate does not overlap with an orthographic projection of the third via hole on the base substrate.

### Claim 17

A display device, comprising a display substrate, wherein the display substrate comprises:
a base substrate; and
a gate driving circuit provided on a peripheral region of the base substrate, wherein the gate driving circuit comprises a plurality of shift register circuits that are arranged in a first direction,
each shift register circuit comprises an input circuit, a control circuit, an output circuit and an output noise reduction circuit,
the input circuit is connected to an input terminal and configured to control a level of a first node in response to an input signal that is input by the input terminal,
the control circuit is connected to the first node, a second node and a third node,
the output circuit is connected to the third node and an output terminal, respectively, and is configured to provide an output signal to the output terminal,
the output noise reduction circuit is connected to the second node and the output terminal, respectively, and is configured for noise reduction on the output terminal,
the control circuit comprises a first transistor, a second transistor and a third transistor,
a first electrode of the first transistor is directly connected to the second node and configured to control a level of the second node,
a first electrode of the second transistor is connected to the third node, a second electrode of the second transistor is connected to a first voltage line to receive a first voltage, a gate electrode of the second transistor is directly connected to the first node, and the second transistor is configured to control a level of the third node in response to the level of the first node,
a first electrode of the third transistor is connected to the third node and configured to control the level of the third node, and
at least two selected from group consisting of an active layer of the first transistor, an active layer of the second transistor and an active layer of the third transistor extend in the first direction and are sequentially arranged in the first direction,
wherein the control circuit further comprises: a fourth transistor and a fifth transistor,
a first electrode of the fourth transistor is connected to the first voltage line to receive the first voltage, a second electrode of the fourth transistor is connected to the second node, a gate electrode of the fourth transistor is connected to a first control node, and the fourth transistor is configured to control the level of the second node in response to a level of the first control node;
a first electrode of the fifth transistor is connected to the first voltage line to receive the first voltage, a second electrode of the fifth transistor is connected to the second node, a gate electrode of the fifth transistor is connected to a reset signal line, and the fifth transistor is configured to reset the second node; and
an active layer of the fourth transistor and an active layer of the fifth transistor extend in the first direction, respectively, and are arranged along a second direction, and the second direction intersects with the first direction.

### Claim 18

A display substrate, comprising:
a base substrate; and
a gate driving circuit provided on a peripheral region of the base substrate, wherein the gate driving circuit comprises a plurality of shift register circuits that are arranged in a first direction,
each shift register circuit comprises an input circuit, a control circuit, an output circuit and an output noise reduction circuit,
the input circuit is connected to an input terminal and configured to control a level of a first node in response to an input signal that is input by the input terminal,
the control circuit is connected to the first node, a second node and a third node,
the output circuit is connected to the third node and an output terminal, respectively, and is configured to provide an output signal to the output terminal,
the output noise reduction circuit is connected to the second node and the output terminal, respectively, and is configured for noise reduction on the output terminal,
the control circuit comprises a first transistor, a second transistor and a third transistor,
a first electrode of the first transistor is connected to the second node and configured to control a level of the second node,
a first electrode of the second transistor is connected to the third node, a second electrode of the second transistor is connected to a first voltage line to receive a first voltage, a gate electrode of the second transistor is connected to the first node, and the second transistor is configured to control a level of the third node in response to the level of the first node,
a first electrode of the third transistor is connected to the third node and configured to control the level of the third node, and
at least two selected from group consisting of an active layer of the first transistor, an active layer of the second transistor and an active layer of the third transistor extend in the first direction and are sequentially arranged in the first direction,
wherein the control circuit further comprises: a fourth transistor and a fifth transistor,
a first electrode of the fourth transistor is connected to the first voltage line to receive the first voltage, a second electrode of the fourth transistor is connected to the second node, a gate electrode of the fourth transistor is connected to a first control node, and the fourth transistor is configured to control the level of the second node in response to a level of the first control node;
a first electrode of the fifth transistor is connected to the first voltage line to receive the first voltage, a second electrode of the fifth transistor is connected to the second node, a gate electrode of the fifth transistor is connected to a reset signal line, and the fifth transistor is configured to reset the second node; and
an active layer of the fourth transistor and an active layer of the fifth transistor extend in the first direction, respectively, and are arranged along a second direction, and the second direction intersects with the first direction.