Semiconductor apparatus, display device, and electronic device

A display device comprising:

• a first block;
• a second block;
• a third block;
• a first switch circuit;
• and
• a pixel,
• wherein the first block, the second block, and the third block each include a plurality of flip-flop circuits and a plurality of output circuits,
• wherein a first pair of output circuits of the plurality of output circuits is electrically connected to a first flip-flop circuit of the plurality of flip-flop circuits,
• wherein a second pair of output circuits of the plurality of output circuits is electrically connected to a second flip-flop circuit of the plurality of flip-flop circuits,
• wherein in each of the first block, the second block, and the third block, the plurality of flip-flop circuits are provided so as to form a cascade,
• wherein a flip-flop circuit of the plurality of flip-flop circuits in the last stage of the first block, a flip-flop circuit of the plurality of flip-flop circuits in a first stage of the second block, a flip-flop circuit of the plurality of flip-flop circuits in the last stage of the second block, and a flip-flop circuit of the plurality of flip-flop circuits in a first stage of the third block are electrically connected to the first switch circuit,
• wherein one output circuit of the first pair of output circuits includes a second switch circuit, a first circuit, and a second circuit,
• wherein the first flip-flop circuit is electrically connected to a first switch of the second switch circuit and a second switch of the second switch circuit,
• wherein the first switch is electrically connected to the first circuit and the second switch is electrically connected to the second circuit,
• wherein a pulse width control signal is input to a third switch of the second switch circuit and a fourth switch of the second switch circuit,
• wherein the third switch is electrically connected to the first circuit and the fourth switch is electrically connected to the second circuit,
• wherein the pixel includes a third circuit including a display element and a fourth circuit including a light-receiving element, and
• wherein the first circuit is electrically connected to the third circuit and the second circuit is electrically connected to the fourth circuit.

A semiconductor apparatus comprising:

• a first block;
• a second block;
• a third block;
• and
• a first switch circuit,
• wherein the first block, the second block, and the third block each include a plurality of flip-flop circuits and a plurality of output circuits,
• wherein a first pair of output circuits of the plurality of output circuits is electrically connected to a first flip-flop circuit of the plurality of flip-flop circuits,
• wherein a second pair of output circuits of the plurality of output circuits is electrically connected to a second flip-flop circuit of the plurality of flip-flop circuits,
• wherein in each of the first block, the second block, and the third block, the plurality of flip-flop circuits are provided so as to form a cascade,
• wherein a flip-flop circuit of the plurality of flip-flop circuits in the last stage of the first block, a flip-flop circuit of the plurality of flip-flop circuits in a first stage of the second block, a flip-flop circuit of the plurality of flip-flop circuits in the last stage of the second block, and a flip-flop circuit of the plurality of flip-flop circuits in a first stage of the third block are electrically connected to the first switch circuit,
• wherein one output circuit of the first pair of output circuits includes a second switch circuit, a first circuit, and a second circuit,
• wherein the first flip-flop circuit is electrically connected to a first switch of the second switch circuit and a second switch of the second switch circuit,
• wherein the first switch is electrically connected to the first circuit and the second switch is electrically connected to the second circuit,
• wherein a pulse width control signal is input to a third switch of the second switch circuit and a fourth switch of the second switch circuit,
• wherein the third switch is electrically connected to the first circuit and the fourth switch is electrically connected to the second circuit,
• wherein the third switch is a first transistor and the fourth switch is a second transistor,
• wherein a gate of the first transistor is electrically connected to a first electrode of a first capacitor,
• wherein one of a source and a drain of the first transistor is electrically connected to a second electrode of the first capacitor and one of a source and a drain of a third transistor of the first circuit,
• wherein a gate of the second transistor is electrically connected to a first electrode of a second capacitor, and
• wherein one of a source and a drain of the second transistor is electrically connected to a second electrode of the second capacitor and one of a source and a drain of a fourth transistor of the second circuit.