Back to results
US 12,682,817 B2Granted
Scan driving circuit and display panel
AssigneeEverDisplay Optronics (Shanghai) Limited
InventorsYing-Hsiang Tseng, Lina Xiao, Qi Wang, Jie Liu
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to the field of display panels and provides a scan driving circuit and a display panel. The scan driving circuit includes multiple stages of shift register units and a timing controller. Each stage of shift register unit includes 10 or 11 transistors and 2 capacitors. The timing controller includes three timing control signal lines.
Claims20
A scan driving circuit, comprising multiple stages of shift register units, wherein each of the shift register units comprises:
- a first transistor, wherein a first electrode of the first transistor is connected to a third node, a second electrode of the first transistor is connected to a signal input terminal, and a gate electrode of the first transistor is connected to a third timing control terminal;
- a second transistor, wherein a first electrode of the second transistor is connected to a first power supply, a second electrode of the second transistor is connected to the third node, and a gate electrode of the second transistor is connected to a first timing control terminal;
- a third transistor, wherein a first electrode of the third transistor is connected to the third timing control terminal, a second electrode of the third transistor is connected to a first node, and a gate electrode of the third transistor is connected to the third node;
- a fourth transistor, wherein a first electrode of the fourth transistor is connected to the third node, a second electrode of the fourth transistor is connected to a second node, and a gate electrode of the fourth transistor is connected to a second power supply;
- a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power supply, and a gate electrode of the fifth transistor is connected to a second timing control terminal;
- a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the fifth transistor, a second electrode of the sixth transistor is connected to the second node, and a gate electrode of the sixth transistor is connected to the first node;
- a seventh transistor, wherein a second electrode of the seventh transistor is connected to the second power supply, and a gate electrode of the seventh transistor is connected to the first timing control terminal;
- an eighth transistor, wherein a first electrode of the eighth transistor is connected to the first node, a second electrode of the eighth transistor is connected to the second power supply, and a gate electrode of the eighth transistor is connected to the third timing control terminal;
- a ninth transistor, wherein a first electrode of the ninth transistor is connected to the first power supply, a second electrode of the ninth transistor is connected to a signal output terminal, and a gate electrode of the ninth transistor is connected to the first node;
- a tenth transistor, wherein a first electrode of the tenth transistor is connected to the signal output terminal, a second electrode of the tenth transistor is connected to the second timing control terminal, and a gate electrode of the tenth transistor is connected to the second node;
- a first capacitor, wherein a first electrode of the first capacitor is connected to the first power supply, and a second electrode of the first capacitor is connected to the first node;
- and
- a second capacitor, wherein a first electrode of the second capacitor is connected to the second node, and a second electrode of the second capacitor is connected to the signal output terminal.
10 more elements
A display panel, comprising a scan driving circuit, wherein the scan driving circuit comprises multiple stages of shift register units, and each of the shift register units comprises:
- a first transistor, wherein a first electrode of the first transistor is connected to a third node, a second electrode of the first transistor is connected to a signal input terminal, and a gate electrode of the first transistor is connected to a third timing control terminal;
- a second transistor, wherein a first electrode of the second transistor is connected to a first power supply, a second electrode of the second transistor is connected to the third node, and a gate electrode of the second transistor is connected to a first timing control terminal;
- a third transistor, wherein a first electrode of the third transistor is connected to the third timing control terminal, a second electrode of the third transistor is connected to a first node, and a gate electrode of the third transistor is connected to the third node;
- a fourth transistor, wherein a first electrode of the fourth transistor is connected to the third node, a second electrode of the fourth transistor is connected to a second node, and a gate electrode of the fourth transistor is connected to a second power supply;
- a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power supply, and a gate electrode of the fifth transistor is connected to a second timing control terminal;
- a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the fifth transistor, a second electrode of the sixth transistor is connected to the second node, and a gate electrode of the sixth transistor is connected to the first node;
- a seventh transistor, wherein a second electrode of the seventh transistor is connected to the second power supply, and a gate electrode of the seventh transistor is connected to the first timing control terminal;
- an eighth transistor, wherein a first electrode of the eighth transistor is connected to the first node, a second electrode of the eighth transistor is connected to the second power supply, and a gate electrode of the eighth transistor is connected to the third timing control terminal;
- a ninth transistor, wherein a first electrode of the ninth transistor is connected to the first power supply, a second electrode of the ninth transistor is connected to a signal output terminal, and a gate electrode of the ninth transistor is connected to the first node;
- a tenth transistor, wherein a first electrode of the tenth transistor is connected to the signal output terminal, a second electrode of the tenth transistor is connected to the second timing control terminal, and a gate electrode of the tenth transistor is connected to the second node;
- a first capacitor, wherein a first electrode of the first capacitor is connected to the first power supply, and a second electrode of the first capacitor is connected to the first node;
- and
- a second capacitor, wherein a first electrode of the second capacitor is connected to the second node, and a second electrode of the second capacitor is connected to the signal output terminal.
10 more elements
Dependencies are inferred from the claim text.