Multi-phase linear dithering systems and methods

Image processing circuitry configured to:

• receive input image data in a non-linear color space at a first bit-depth;
• truncate one or more least-significant-digits (LSBs) of the input image data, generating truncated image data at a second bit-depth less than the first bit-depth;
• determine an alpha value indicative of how many pixel locations of a block of pixels to which an increase in gray level is to be applied based on an input pixel value of the input image data corresponding to a pixel of interest within the block of pixels, wherein the alpha value is based on the input pixel value and a number corresponding to how many LSBs are truncated from the input image data;
• determine an arrangement of the pixel locations within the block of pixels based on respective rankings of the pixel locations, wherein the respective rankings are based on one or more phase sets, each phase set of the one or more phase sets comprising an ordered arrangement of indexing numbers;
• and
• apply the increase in the gray level to pixel values of the truncated image data corresponding to the pixel locations to generate dithered image data at the second bit-depth.

A non-transitory, machine-readable medium comprising instructions, wherein, when executed by one or more processors, the instructions cause the one or more processors to perform operations or to control dither circuitry to perform the operations, wherein the operations comprise:

• receiving input image data in a non-linear color space at a first bit-depth;
• truncating one or more least-significant-digits (LSBs) of the input image data, generating truncated image data;
• determining an alpha value indicative of how many pixel locations of a block of pixels to which an increase in gray level is to be applied based on an input pixel value of the input image data corresponding to a pixel of interest within the block of pixels, wherein the alpha value corresponds to a ratio of gray levels in a linear color space that equates to a luminance level of the input pixel value at the first bit-depth;
• and
• applying the increase in the gray level to pixel values of the truncated image data corresponding to the pixel locations to generate dithered image data at a second bit-depth, the second bit-depth is less than the first bit-depth by the one or more LSBs, wherein neither the input image data nor the truncated image data is converted to the linear color space between receiving the input image data and applying the increase in the gray level to the pixel values of the truncated image data corresponding to the pixel locations.

Image processing circuitry comprising:

• linearity circuitry configured to:
• receive input image data in a non-linear color space at a first bit-depth;
• truncate one or more least-significant-digits (LSBs) of the input image data, generating truncated image data at a second bit-depth less than the first bit-depth;
• and
• determine an alpha value indicative of how many pixel locations of a block of pixels to which an increase in gray level is to be applied based on an input pixel value of the input image data corresponding to a pixel of interest within the block of pixels;
• multi-phase ranking circuitry configured to determine an arrangement of the pixel locations within the block of pixels based on comparisons between respective rankings of the pixel locations and the alpha value, wherein the respective rankings are based on one or more phase sets, each phase set of the one or more phase sets comprising an ordered arrangement of indexing numbers;
• and
• dithering circuitry configured to apply the increase in the gray level to pixel values of the truncated image data corresponding to the pixel locations to generate dithered image data at the second bit-depth.