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US 12,682,141 B2Granted
Scalable, optimal retiming of multi-clocked netlists
AssigneeInternational Business Machines Corporation
InventorsJason Raymond Baumgartner, Rohit Dureja, Raj Kumar Gajavelly, Robert Lowell Kanzelman
Life of this patent
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Abstract
Embodiments of the present disclosure provide enhanced systems and methods for implementing enhanced retiming of multiple clock netlists to improve integrated circuit (IC) design quality and provide enhanced retiming with reduced retiming runtime. Disclosed embodiments provide effective and efficient retiming without sacrificing netlist quality, and yield significant speedup of retiming runtime over traditional retiming.
Claims20
A method comprising:
- importing a netlist for a given integrated circuit (IC) design;
- the netlist comprising clock domain information for multiple clock domains;
- partitioning the netlist into regions with identically clocked registers to create a clock domain partition and a free-running partition for each of the multiple clock domains;
- identifying selected clock domains of the multiple clock domains in the netlist as free-running domains;
- identifying two compatible clock domains based on at least one of symbolic constant registers or free-running domains, and arbitrarily-clocked registers;
- combining the two compatible clock domains to generate at least one of a combined clock domain and free running partition or a combined symbolic-constant register and arbitrarily-clocked partition;
- creating a respective retiming graph for each of the at least one of the combined clock domain and free running partition or the combined symbolic-constant register and arbitrarily-clocked partition and for each clock domain partition of the multiple clock domains modeling at least one clock domain partition as a hypergraph node;
- retiming the respective retiming graphs using a retiming solver, atomically retiming each hypergraph node, to provide a retiming result;
- and
- forming, based on the retiming result, a behaviorally equivalent retimed netlist of the imported netlist.
7 more elements
A system, comprising:
- a processor;
- and
- a memory, wherein the memory includes a computer program product configured to perform operations to implement retiming of multi-clocked netlists, the operations comprising:
- importing a netlist for a given integrated circuit (IC) design;
- the netlist comprising clock domain information for multiple clock domains;
- partitioning the netlist into regions with identically clocked registers to create a clock domain partition and a free-running partition for each of the multiple clock domains;
- identifying selected clock domains of the multiple clock domains in the netlist as free-running domains;
- identifying two compatible clock domains based on at least one of symbolic constant registers or free-running domains, and arbitrarily-clocked registers;
- combining the two compatible clock domains to generate at least one of a combined clock domain and free running partition or a combined symbolic-constant register and arbitrarily-clocked partition;
- creating a respective retiming graph for each of the at least one of the combined clock domain and free running partition or the combined symbolic-constant register and arbitrarily-clocked partition and for each clock domain partition of the multiple clock domains modeling at least one clock domain partition as a hypergraph node;
- retiming the respective retiming graphs using a retiming solver, atomically retiming each hypergraph node, to provide a retiming result;
- and
- forming, based on the retiming result, a behaviorally equivalent retimed netlist of the imported netlist.
10 more elements
A computer program product to implement retiming of multi-clocked netlists, the computer program product comprising:
- a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by one or more computer processors to perform an operation comprising:
- importing a netlist for a given integrated circuit (IC) design;
- the netlist comprising clock domain information for multiple clock domains;
- partitioning the netlist into regions with identically clocked registers to create a clock domain partition and a free-running partition for each of the multiple clock domains;
- identifying selected clock domains of the multiple clock domains in the netlist as free-running domains;
- identifying two compatible clock domains based on at least one of symbolic constant registers or free-running domains, and arbitrarily-clocked registers;
- combining the two compatible clock domains to generate at least one of a combined clock domain and free running partition or a combined symbolic-constant register and arbitrarily-clocked partition;
- creating a respective retiming graph for each of the at least one of the combined clock domain and free running partition or the combined symbolic-constant register and arbitrarily-clocked partition and for each clock domain partition of the multiple clock domains modeling at least one clock domain partition as a hypergraph node;
- retiming the respective retiming graphs using a retiming solver, atomically retiming each hypergraph node, to provide a retiming result;
- and
- forming, based on the retiming result, a behaviorally equivalent retimed netlist of the imported netlist.
8 more elements
Dependencies are inferred from the claim text.