Multi-core system-on-chip

A system-on-chip comprising:

• a first core having a first processor architecture;
• a second core having a second processor architecture, different from the first processor architecture;
• a shared bus, communicatively coupled to the first core and to the second core;
• a shared memory, communicatively coupled to the shared bus, for storing shared data accessible by the first core and by the second core over the shared bus;
• a hardware comparison module comprising circuitry configured to compare first data and second data, the first data determined by one or more operations of the first core, the second data determined by one or more operations of the second core, the circuitry of the hardware comparison module configured to detect an inconsistency between the first data and the second data and to signal when an inconsistency is detected;
• a first comparison-data bus communicatively coupled to the first core and to the hardware comparison module, the first comparison-data bus arranged to provide the first data to the hardware comparison module, wherein the first comparison-data bus is isolated from the shared bus;
• a second comparison-data bus communicatively coupled to the second core and to the hardware comparison module, the second comparison-data bus arranged to provide the second data to the hardware comparison module, wherein the second comparison-data bus is isolated from the shared bus and from the first comparison-data bus;
• and
• a hardware accelerator module arranged between the first core and the first comparison-data bus, the hardware accelerator module comprising circuitry configured to receive commands from the first core over a hardware-accelerator interface, the hardware accelerator module configured to output the first data onto the first comparison-data bus in response to a command from the first core received over the hardware-accelerator interface.