Topology-based dynamic address assignment of semiconductor memory devices
AssigneeMicron Technology, Inc.
InventorJohn Christopher M. Sancon
Life of this patent
Estimating the term…
Abstract
Disclosed are methods, systems, and apparatuses for a topology-based dynamic address assignment (DAA) of semiconductor memory devices (e.g., dynamic random access memory (DRAM)). The memory devices may be connected via a daisy chain arrangement that forms a sideband bus. During a DAA process, the topology-based DAA assigns addresses to the memory devices based on their placement on the daisy chain (e.g., their placement within the topology of the sideband bus). The topology-based DAA described herein may facilitate predictably assigning dynamic addresses to memory devices based on, for example, their position on a memory module.
Claims20
A memory device comprising:
- a memory array;
- a sideband bus interface coupled to a sideband bus, the sideband bus interface comprising:
- an upstream data terminal coupled to an upstream data line;
- and
- a downstream data terminal coupled to a downstream data line, wherein the upstream data line is initially uncoupled communicatively from the downstream data line;
- and
- a topology-based dynamic address assignment (DAA) circuit coupled to the sideband bus interface, wherein the topology-based DAA circuit is configured to:
- determine whether the memory device has been assigned an address;
- and
- couple the upstream data line to the downstream data line when the memory device has been assigned the address, the upstream and downstream data lines coupled for allowing a message to flow across the downstream and upstream data lines regardless of a content of the message.
A memory module comprising:
- a first memory device, the first memory device comprising a first clock terminal, a first upstream data terminal, and a first downstream data terminal;
- a second memory device, the second memory device comprising a second clock terminal, a second upstream data terminal, and a second downstream data terminal;
- a clock line coupled to the first clock terminal and the second clock terminal;
- a first data line segment coupled to the first upstream data terminal;
- and
- a second data line segment coupled to the first downstream data terminal and the second upstream data terminal;
- wherein, prior to an address being assigned to the first memory device, the first upstream data terminal is initially uncoupled from the first downstream data terminal;
- and
- wherein, when the first memory device has been assigned the address, the first memory device is configured to couple the first upstream data terminal to the first downstream data terminal for allowing a message to flow across the first upstream data terminal and the first downstream data terminal regardless of a content of the message.
A method comprising:
- transmitting, by a bus controller coupled to a bus, an enter DAA command over the bus;
- receiving, over the bus, device information from a memory device coupled to the bus;
- maintaining an upstream data terminal of the memory device uncoupled from a downstream data terminal of the memory device until the memory device receives a dynamic address;
- generating, by the bus controller, the dynamic address;
- associating the dynamic address with the received device information;
- transmitting, over the bus, the dynamic address to the memory device;
- coupling, after the memory device receives the dynamic address, the upstream data terminal to the downstream data terminal to allow the dynamic address to flow across the upstream data terminal and the downstream data terminal regardless of a content of the dynamic address;
- and
- transmitting, over the bus, the enter DAA command.
Dependencies are inferred from the claim text.