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US 12,681,872 B2Granted
Memory manager, processor memory subsystem, processor, and electronic device
AssigneeHuawei Technologies Co., Ltd.
InventorWen Yin
Life of this patent
Estimating the term…
Abstract
A memory manager disposed between a memory and a processor. One end of the memory manager is coupled to the processor using a serial line, and the other end of the memory manager is coupled to the memory using a parallel line to provide the processor with a serial interface instead of a parallel interface.
Claims20
A memory manager configured to control data exchange between a processor and a memory, and comprising:
- a parallel interface circuit comprising:
- an internal connection end;
- and
- an external connection end configured to couple to the memory;
- a cache prefetching circuit;
- a memory control circuit coupled to the cache prefetching circuit, configured to control an on state and an off state of the cache prefetching circuit, and comprising:
- a first end;
- and
- a second end coupled to the internal connection end;
- and
- a serial-to-parallel conversion interface circuit comprising:
- a serial end configured to couple to the processor;
- and
- a parallel end coupled to the first end and the internal connection end, wherein the serial-to-parallel conversion interface circuit is configured to:
- receive, from the processor, a serialized memory data write request;
- convert the serialized memory data write request into a parallelized memory data write request;
- and
- send, to the memory control circuit, the parallelized memory data write request, wherein the cache prefetching circuit is coupled to the parallel end of the serial-to-parallel conversion interface circuit and the internal connection end of the parallel interface circuit, and wherein the memory control circuit is further configured to:
- selectively route data between the serial-to-parallel conversion interface circuit and the parallel interface circuit through the cache prefetching circuit in response to the cache prefetching circuit being in the on state;
- and
- bypass the cache prefetching circuit such that the parallel interface circuit is directly coupled to the serial-to-parallel conversion interface circuit in response to the cache prefetching circuit being in the off state.
18 more elements
A processor memory subsystem, comprising:
- a first processor comprising a first serial-to-parallel conversion interface circuit having a first serial end;
- a first memory;
- a first memory manager comprising:
- a parallel interface circuit comprising:
- an internal connection end;
- and
- an external connection end configured to couple to the first memory;
- a cache prefetching circuit;
- a memory control circuit coupled to the cache prefetching circuit, configured to control an on state and an off state of the cache prefetching circuit and to control data exchange between the first processor and the first memory, and comprising:
- a first end;
- and
- a second end coupled to the internal connection end;
- and
- a second serial-to-parallel conversion interface circuit comprising:
- a second serial end configured to couple to the first serial end;
- and
- a parallel end coupled to the first end and the internal connection end,
- wherein the cache prefetching circuit is coupled to the parallel end of the serial-to-parallel conversion interface circuit and the internal connection end of the parallel interface circuit, and
- wherein the memory control circuit is further configured to:
- selectively route data between the serial-to-parallel conversion interface circuit and the parallel interface circuit through the cache prefetching circuit in response to the cache prefetching circuit being in the on state;
- and
- bypass the cache prefetching circuit such that the parallel interface circuit is directly coupled to the serial-to-parallel conversion interface circuit in response to the cache prefetching circuit being in the off state;
- a second processor is configured to send, using an input/output interface circuit, a parallelized memory data write request to a third processor, wherein the third processor comprises a third serial-to-parallel conversion interface circuit and is configured to:
- convert, using the third serial-to-parallel conversion interface circuit, the parallelized memory data write request into a serialized memory data write request;
- and
- send, to a second memory manager and corresponding to the third processor, the serialized memory data write request.
23 more elements
An electronic device comprising:
- a processor memory subsystem comprising:
- a processor comprising a first serial-to-parallel conversion interface circuit having a first serial end;
- a memory;
- and
- a memory manager comprising:
- a parallel interface circuit comprising:
- an internal connection end;
- and
- an external connection end configured to couple to the memory;
- a cache prefetching circuit;
- a memory control circuit coupled to the cache prefetching circuit, configured to control an on state and an off state of the cache prefetching circuit and to control data exchange between the processor and the memory, wherein the memory control circuit comprises:
- a first end;
- and
- a second end coupled to the internal connection end;
- and
- a serial-to-parallel conversion interface circuit comprising:
- a second serial end configured to couple to the first serial end;
- and
- a parallel end coupled to the first end and the internal connection end,
- wherein the serial-to-parallel conversion interface circuit is configured to:
- receive, from the processor, a serialized memory data write request;
- convert the serialized memory data write request into a parallelized memory data write request;
- and
- send, to the memory control circuit, the parallelized memory data write request,
- wherein the cache prefetching circuit is coupled to the parallel end of the serial-to-parallel conversion interface circuit and the internal connection end of the parallel interface circuit, and
- wherein the memory control circuit is further configured to:
- selectively route data between the serial-to-parallel conversion interface circuit and the parallel interface circuit through the cache prefetching circuit in response to the cache prefetching circuit being in the on state;
- and
- bypass the cache prefetching circuit such that the parallel interface circuit is directly coupled to the serial-to-parallel conversion interface circuit in response to the cache prefetching circuit being in the off state.
26 more elements
Dependencies are inferred from the claim text.