Processors with toggleable memory tagging extensions and related methods
AssigneeAmpere Computing LLC
InventorsBret Leslie Toll, Benjamin Crawford Chaffin, Jonathan Christopher Perry, David Paul Turley
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AssigneeAmpere Computing LLC
InventorsBret Leslie Toll, Benjamin Crawford Chaffin, Jonathan Christopher Perry, David Paul Turley
Estimating the term…
In processors that include a memory tagging extension (MTE), before reading data from or writing data into a memory address, tag bits associated with the memory address are read from the memory and compared to tag bits in the instruction target address. This delays memory write instructions that would not otherwise have to perform a read from the memory circuit before executing the write operation (e.g., full cache line writes), reducing processor performance. An exemplary processing circuit includes a toggleable MTE to provide access to a memory circuit in one of a first mode, in which a memory tagging extension is enabled, and a second mode, in which the MTE is disabled. The processing circuit includes an execution circuit to process a memory instruction and a load/store circuit that does not read the tag bits when MTE is disabled, thereby reducing execution time of the memory instruction.
A processing circuit configured to couple to a memory circuit, the processing circuit comprising:
A method in a processing circuit configured to couple to a memory circuit, the method comprising:
A processor-based system comprising:
Dependencies are inferred from the claim text.