Hardware-based trace assist unit

A method of operating a hardware-based trace assist unit (TAU), the method comprising:

• receiving, using loading circuitry of the TAU, a trace event from one of a plurality of processor cores, the trace event having a category from a plurality of predefined categories;
• determining, using the loading circuitry, whether any of a plurality of physical buffers of the TAU are assigned to the category of the trace event;
• when none of the plurality of physical buffers is assigned to the category, assigning one of the plurality of physical buffers to the category;
• writing the trace event to a first physical buffer, of the plurality of physical buffers, that is assigned to the category;
• and
• transmitting, responsive to one or more predefined conditions, an unload signal to unloading circuitry of the TAU to unload contents of the first physical buffer to an external memory.

A computing system comprising:

• a plurality of processor cores;
• a cache;
• and
• a trace assist unit operable with the plurality of processor cores and comprising a plurality of physical buffers and loading circuitry and unloading circuitry that are communicatively coupled with the plurality of physical buffers, the trace assist unit to:
• receive trace events from various ones of the plurality of processor cores, each of the trace events having a respective category from a plurality of predefined categories;
• determine, for one of the trace events, that none of the plurality of physical buffers is assigned to the respective category of the one trace event and dynamically assign one of the plurality of physical buffers to the respective category of the one trace event;
• write the trace events to respective ones of a plurality of physical buffers of the trace assist unit, wherein the plurality of physical buffers are assigned to the respective categories of the plurality of predefined categories;
• and
• unload, responsive to one or more predefined conditions, contents of a selected physical buffer of the plurality of physical buffers to the cache.