Test method and system based on variable combination time sequence function coverage

A test method based on a variable combination time sequence function coverage, comprising:

• constructing a variable combination time sequence function coverage structure based on an actual verification requirement, and using the variable combination time sequence function coverage structure as a random constraint, wherein the variable combination time sequence function coverage structure is used to represent a relationship in which a single variable varies with time or a relationship in which a combination of at least two variables varies with time;
• determining a random seed of each value range of each variable in the variable combination time sequence function coverage structure;
• sequentially obtaining a time point as a current time point based on a time sequence of the variable combination time sequence function coverage structure;
• obtaining a value segment of each variable at the current time point from the variable combination time sequence function coverage structure, to form a variable combination structure at the current time point;
• for the variable combination structure at the current time point, generating a random excitation of each variable based on a corresponding random seed to perform testing in a current scenario for chip verification;
• and
• repeating the steps of sequentially obtaining a time point as a current time point based on a time sequence of the variable combination time sequence function coverage structure, obtaining a value segment of each variable at the current time point from the variable combination time sequence function coverage structure, to form a variable combination structure at the current time point, and for the variable combination structure at the current time point, generating a random excitation of each variable based on a corresponding random seed to perform testing in a current scenario for chip verification, until the entire time sequence is traversed;
• wherein the method further comprises:
• outputting a test result of a chip to be verified;
• wherein the random seed is used to ensure that a random excitation generated in each test is capable of being reproduced.