Scalable hardware FIFO

A first-in-first-out (FIFO) device, comprising:

• a plurality of FIFO stages coupled in series, wherein each of the FIFO stages includes:
• a data register representing a FIFO entry;
• a valid register operable to store a data valid signal to provide a valid signal indicating whether the data register of a corresponding FIFO stage is storing valid data;
• and
• a control circuit operable to generate the data valid signal for the corresponding FIFO stage, and a load signal to control data loading into the data register of the corresponding FIFO stage,
• wherein the control circuit of each intermediate FIFO stage having a preceding FIFO stage and a subsequent FIFO stage is operable to generate the load signal based on:
• valid signals of the intermediate FIFO stage, the preceding FIFO stage, and the subsequent FIFO stage;
• a push signal to load input data into the FIFO device;
• and
• a pop signal to provide output data from the FIFO device, and
• wherein the control circuit of each intermediate FIFO stage having the preceding FIFO stage and the subsequent FIFO stage is further operable to generate the data valid signal for the corresponding FIFO stage when:
• the push signal is asserted, and the valid signal of the preceding FIFO stage indicates that valid data is stored in the preceding FIFO stage, or
• the pop signal is asserted, and the valid signal of the subsequent FIFO stage indicates that valid data is stored in the subsequent FIFO stage.

A method, comprising:

• receiving a push signal to store input data into a first-in-first-out (FIFO) device comprising a plurality of FIFO stages coupled in series, wherein each of the FIFO stages includes a data register representing a FIFO entry, a valid register to store a data valid signal to provide a valid signal indicating whether the FIFO entry is storing valid data, and an input multiplexer to provide to a FIFO stage;
• upon receiving the push signal, determining by the FIFO stage of the FIFO device whether to update the data register of the FIFO stage based on respective valid signals from the FIFO stage, and neighboring FIFO stages of the FIFO stage;
• and
• upon receiving a pop signal to provide output data from the FIFO device, determining by the FIFO stage whether to provide data stored in the data register of the FIFO stage to the preceding FIFO stage based on the valid signal from the FIFO stage, wherein a control circuit of each intermediate FIFO stage having a preceding FIFO stage and a subsequent FIFO stage generates the data valid signal for the corresponding FIFO stage when:
• the push signal is asserted, and the valid signal of the preceding FIFO stage indicates that valid data is stored in the preceding FIFO stage, or
• the pop signal is asserted, and the valid signal of the subsequent FIFO stage indicates that valid data is stored in the subsequent FIFO stage.