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US 12,681,081 B2Granted
Jitter measuring circuit, jitter analyzing apparatus including the same, and related methods of manufacturing semiconductor devices
AssigneeSamsung Electronics Co., Ltd.
InventorsHyeon Gwan Oh, Beomsang Yoo
Life of this patent
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Abstract
A jitter analyzing apparatus may include a first delay circuit configured to delay a reference clock to output a first clock, a second delay circuit configured to delay the reference clock to output a second clock having a delay value greater than the first delay circuit, and a test device configured to measure a jitter component of the first and second delay circuits by measuring the first clock and the second clock.
Claims20
A jitter analyzing apparatus comprising:
- a first delay circuit configured to delay a reference clock to output a first clock;
- a second delay circuit configured to delay the reference clock to output a second clock and have a delay value greater than the first delay circuit;
- and
- a test device configured to measure a jitter component of the first and second delay circuits by measuring the first clock and the second clock.
1 more element
A jitter measuring circuit comprising:
- a first delay circuit comprising a plurality of first logic gates connected in series, and configured to output a first clock by delaying a reference clock through the plurality of first logic gates;
- a second delay circuit comprising a plurality of second logic gates connected in series, and configured to output a second clock by delaying the reference clock through the plurality of second logic gates, a number of second logic gates being greater than a number of first logic gates;
- a first output driver configured to output the first clock to a test device;
- and
- a second output driver configured to output the second clock to the test device,
- wherein the jitter measuring circuit is configured to measure a jitter component of a single logic gate of the plurality of first and second logic gates based on the first clock and the second clock.
3 more elements
A method of manufacturing a semiconductor device including a jitter analyzing apparatus, the method comprising:
- analyzing jitter by using the jitter analyzing apparatus, the analyzing jitter comprising:
- outputting a first clock by delaying a reference clock through a first number of logic gates;
- outputting a second clock by delaying the reference clock through a second number of logic gates, the second number being greater than the first number;
- calculating first measurement values by measuring a time at which an edge of the first clock becomes a predetermined level;
- calculating second measurement values by measuring a time at which an edge of the second clock becomes the predetermined level;
- and
- analyzing a jitter component of a single logic gate of the first and second numbers of logic gates based on the first measurement values, the second measurement values, the first number, and the second number;
- and
- forming the semiconductor device based on the jitter component of the single logic gate.
6 more elements
Dependencies are inferred from the claim text.