High voltage integrated circuit testing interface assembly
AssigneeTexas Instruments Incorporated
InventorsMing-Chuan You, Andrew Patrick Couch, Phillip Marcus Blitz, Xinkun Huang, Chi-Tsung Lee, Roy Deidrick Solomon, Enis Tuncer
Life of this patent
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Abstract
An integrated circuit testing assembly that includes: (i) a first slug configured to contact a first surface of a first set of pins of an integrated circuit; (ii) a second slug configured to contact a second surface of the first set of pins of the integrated circuit; (iii) a third slug configured to contact a first surface of a second set of pins of the integrated circuit; and (iv) a fourth slug configured to contact a second surface of the second set of pins of the integrated circuit.
Claims23
An integrated circuit testing interface system, comprising:
- a first slug configured to contact a first surface of a first set of pins of an integrated circuit;
- a second slug configured to contact a second surface of the first set of pins of the integrated circuit;
- a third slug configured to contact a first surface of a second set of pins of the integrated circuit;
- and
- a fourth slug configured to contact a second surface of the second set of pins of the integrated circuit.
An integrated circuit testing interface system, comprising:
- a first slug configured to contact a first surface of a first set of pins of an integrated circuit;
- a second slug configured to contact a second surface of the first set of pins of the integrated circuit;
- a third slug configured to contact a first surface of a second set of pins of the integrated circuit;
- a fourth slug configured to contact a second surface of the second set of pins of the integrated circuit;
- a first charge separation member between the first slug and the third slug;
- and
- a first hollow dielectric cylinder coupled between the first charge separation member and a first surface of the integrated circuit.
An integrated circuit testing interface system, comprising:
- a first slug configured to contact a first surface of a first set of pins of an integrated circuit;
- a second slug configured to contact a second surface of the first set of pins of the integrated circuit;
- a third slug configured to contact a first surface of a second set of pins of the integrated circuit;
- a fourth slug configured to contact a second surface of the second set of pins of the integrated circuit;
- a first charge separation member between the first slug and the third slug;
- a second charge separation member between the second slug and the fourth slug;
- and
- a first hollow dielectric cylinder coupled between the first charge separation member and a first surface of the integrated circuit;
- and
- a second hollow dielectric cylinder coupled between the second charge separation member and a second surface of the integrated circuit.
An integrated circuit testing interface system, comprising:
- a frame, the frame including metal and dielectric sidewalls;
- and
- a plurality of integrated circuit test sites coupled to the frame, wherein each test site in the plurality of integrated circuit test sites includes a respective slab and a respective pair of electrodes;
- and
- a charge separation member between the electrodes.
An integrated circuit testing interface system, comprising:
- a frame, the frame including metal and dielectric sidewalls;
- a plurality of integrated circuit test sites coupled to the frame;
- wherein each test site in the plurality of integrated circuit test sites includes a respective slab and a respective pair of electrodes;
- and
- wherein the respective pair of electrodes include a structure extending above a first surface and a second surface, opposite the first surface, of the respective slab, and each test site in the plurality of integrated circuit test sites includes:
- a first insulating wall surrounding a majority of the structure extending above the first surface of the respective slab;
- and
- a second insulating wall surrounding a majority of the structure extending above the second surface of the respective slab.
An integrated circuit testing interface system, comprising:
- a frame;
- and
- a plurality of integrated circuit test sites coupled to the frame, each test site in the plurality of integrated circuit test sites including:
- a respective slab;
- a respective pair of electrodes;
- a respective pair of springs, each spring in the respective pair of springs configured to spring bias a respective electrode in the respective pair of electrodes relative to the respective slab;
- and
- a respective pair of metal sleeves, each sleeve in the respective pair of metal sleeves surrounding a respective spring in the respective pair of springs.
Dependencies are inferred from the claim text.