Structure for monitoring hybrid bonds in a semiconductor chip package

A semiconductor structure comprising:

• first, second, and third semiconductor builds;
• wherein the first semiconductor build has a back end of the line having a dielectric stack, metal wiring lines, vias, joining pads and has hybrid bonds to the third semiconductor build for making electrical interconnections,
• wherein the second semiconductor build has a back end of the line having a dielectric stack, metal wiring lines, vias, joining pads and has hybrid bonds to the third semiconductor build for making electrical interconnections,
• a first conductive path passing through certain hybrid bonds of said first semiconductor build to said third semiconductor build and back to said first semiconductor build, and
• a second conductive path passing through certain hybrid bonds of said second semiconductor build to said third semiconductor build and back to said second semiconductor build,
• wherein said first and second conductive paths coupled in series between a first and second terminal, and
• a sensor for measuring the resistance/conductance from said first terminal to said second terminal and generating a signal in response to said resistance/conductance.

A method for fabricating a semiconductor structure comprising the steps of:

• selecting first and second semiconductor builds each having a semiconductor substrate and a BEOL built up to a last layer,
• selecting a third semiconductor build having a semiconductor substrate and a BEOL built up to a last layer and contains a plurality of through silicon vias,
• applying a hybrid bond joining/layer interface on the BEOLs of the first, second and third semiconductor builds,
• positioning and aligning the hybrid bond joining/layers of the first and second semiconductor builds above the hybrid bond joining/layer of the third semiconductor build,
• applying a thermal treatment and anneal to the hybrid bond joining/layers of the first, second and third semiconductor builds thereby bonding the first and second semiconductor builds to the third semiconductor build,
• applying an over-mold over and in between the first, second and third semiconductor builds,
• flipping over and selectively etching the exposed semiconductor substrate backside of the third semiconductor build to remove a portion of the semiconductor substrate to expose the ends of the plurality of through silicon vias,
• forming an insulation layer, solder bump pads and solder bumps above the plurality of through silicon vias, and
• separating respective dies from the wafer.