Thin film transistor array substrate including oxide semiconductor pattern and display device including the same

A thin film transistor array substrate comprising:

• a substrate comprising an active area and a non-active area disposed around the active area;
• a first thin film transistor disposed on the substrate;
• a second thin film transistor disposed on the substrate;
• and
• a third thin film transistor disposed on the substrate,
• wherein the first thin film transistor comprises:
• a first oxide semiconductor pattern disposed over the substrate;
• a first gate electrode disposed under the first oxide semiconductor pattern while overlapping with the first oxide semiconductor pattern;
• a first source electrode and a first drain electrode disposed over and connected to the first oxide semiconductor pattern;
• and
• a first light shielding pattern disposed over the first oxide semiconductor pattern while overlapping with the first oxide semiconductor pattern, the first light shielding pattern being connected to one of the first source electrode and the first drain electrode,
• wherein at least one of the first gate electrode or the first light shielding pattern comprises a semiconductor material layer, and
• wherein the second thin film transistor comprises:
• a second oxide semiconductor pattern disposed over the substrate;
• a second gate electrode disposed under the second oxide semiconductor pattern while overlapping with the second oxide semiconductor pattern;
• a second source electrode and a second drain electrode disposed over and connected to the second oxide semiconductor pattern;
• and
• a second light shielding patter disposed over the second oxide semiconductor pattern while overlapping with the second oxide semiconductor pattern, and
• wherein the third thin film transistor comprises:
• a polycrystalline semiconductor pattern disposed on the substrate;
• a third gate electrode disposed over the polycrystalline semiconductor pattern while overlapping with the polycrystalline semiconductor pattern;
• and
• a third source electrode and a third drain electrode disposed over and connected to the polycrystalline semiconductor pattern.

A display device comprising:

• a thin film transistor array substrate including a light emitting device part connected to a first thin film transistor,
• wherein the light emitting device part comprises an anode connected to a first drain electrode, a cathode corresponding to the anode, and an organic light emitting layer disposed between the anode and the cathode,
• wherein the thin film transistor array substrate comprises:
• a substrate comprising an active area and a non-active area disposed around the active area;
• and
• the first thin film transistor disposed on the substrate,
• wherein the first thin film transistor comprises:
• a first oxide semiconductor pattern disposed over the substrate;
• a first gate electrode disposed under the first oxide semiconductor pattern while overlapping with the first oxide semiconductor pattern;
• a first source electrode and the first drain electrode disposed over and connected to the first oxide semiconductor pattern;
• and
• a first light shielding pattern disposed over the first oxide semiconductor pattern while overlapping with the first oxide semiconductor pattern, the first light shielding pattern being connected to one of the first source electrode and the first drain electrode, wherein a first distance between the first oxide semiconductor pattern and the first light shielding pattern is smaller than a second distance between the first oxide semiconductor pattern and the first gate electrode.

A method of forming a light emitting device, comprising:

• depositing a buffer layer over an entire region of a substrate;
• forming a first metal material layer, wherein the first metal layer includes a plurality of gate electrodes;
• depositing a first gate insulating layer over the entire region including the plurality of gate electrodes;
• forming a polycrystalline semiconductor pattern on the first gate insulating layer;
• implanting ions of the polycrystalline semiconductor pattern to create conductive portions of the polycrystalline semiconductor pattern using the plurality of gate electrodes as an alignment mask;
• depositing a second gate insulating layer over the entire region including the polycrystalline semiconductor pattern;
• forming a first light shielding pattern over each region corresponding to a light emitting device;
• forming source electrodes and gate electrodes over the first light shielding pattern, wherein each first light shielding pattern is coupled to a corresponding source electrode or gate electrode to increase a capacitance associated with at least one active device;
• and
• forming a plurality of light emitting devices over the source electrodes and the gate electrodes.