Selective capping of contact layer for CMOS devices

A method of forming an electrical contact in a semiconductor structure, comprising:

• performing a pre-clean process on surfaces of a semiconductor structure comprising a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region;
• performing a patterning process to form a hard mask on the semiconductor structure, wherein the hard mask covers the surface of the first semiconductor region within the first opening and exposes the surface of the second semiconductor region within the second opening;
• performing an etch process to form a groove at the exposed surface of the second semiconductor region;
• performing a first selective deposition process to form a contact layer on the exposed surface of the second semiconductor region within the second opening;
• performing a second selective deposition process to form a cap layer on the contact layer;
• performing a removal process to remove the hard mask and expose the surface of the first semiconductor region within the first opening;
• performing a third selective deposition process to form a metal layer on the exposed surface of the first semiconductor region and the cap layer;
• and
• performing a metal fill process to form a first contact plug in the first opening and a second contact plug in the second opening.

A processing system, comprising:

• a first processing chamber;
• a second processing chamber;
• a third processing chamber;
• and
• a system controller configured to cause the processing system to:
• perform, in the first processing chamber, a patterning process to form a hard mask on a semiconductor structure comprising a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, wherein the hard mask covers on a surface of the first semiconductor region within the first opening and exposes a surface of the second semiconductor region within the second opening;
• perform, in the second processing chamber, a first selective deposition process to form a contact layer on the exposed surface of the second semiconductor region within the second opening;
• and
• perform, in the third processing chamber, a second selective deposition process to form a cap layer on the contact layer.