US 12,677,464 B2 · Semiconductor devices having vertical field effect transistors

Abstract

A semiconductor structure includes a first upper source/drain region, a second upper source/drain region, a first lower source/drain contact, a second lower source/drain contact, and a third conductive region. The first upper source/drain contact is disposed at a first elevation. The second upper source/drain contact is disposed at the first elevation. The first lower source/drain contact is disposed at a second elevation. The second lower source/drain contact is disposed at the second elevation. The third conductive region is disposed at a third elevation. A projection area of the third conductive region is disposed between a projection area of the first upper source/drain contact and a projection area of the second upper source/drain contact. The third elevation is disposed between the first elevation and the second elevation.

Claims20

Dependent claims

A semiconductor structure comprising:

a first upper source/drain contact disposed at a first elevation;
a second upper source/drain contact disposed at the first elevation;
a first lower source/drain contact disposed at a second elevation;
a second lower source/drain contact disposed at the second elevation;
and
a third conductive region disposed at a third elevation, wherein a projection area of the third conductive region is disposed between a projection area of the first upper source/drain contact and a projection area of the second upper source/drain region, and wherein the third elevation is disposed between the first elevation and the second elevation.

3 more elements

A semiconductor structure comprising:

a first VFET structure, wherein the first VFET structure comprises a first upper source/drain contact;
a second VFET structure adjacent to the first VFET structure, wherein the second VFET structure comprises a second upper source/drain contact;
and
a third conductive region, wherein a projection area of the third conductive region is disposed between a projection area of the first upper source/drain contact and a projection area of the second upper source/drain contact, wherein an elevation of the third conductive region is disposed below an elevation of the first upper source/drain contact and the second upper source/drain contact, wherein the first VFET structure further comprises an active/doped region and a first lower source/drain contact, wherein the active/doped region contacts the first upper source/drain contact and the first lower source/drain contact, wherein a third elevation layer comprises a metal gate layer, wherein the metal gate layer contacts the active/doped region and surrounds a portion of the active/doped region.

1 more element

Dependencies are inferred from the claim text.

Semiconductor devices having vertical field effect transistors

Life of this patent

Semiconductor devices having vertical field effect transistors

Life of this patent

Abstract

Claims20