Integrating standard-gate transistors and extended-gate transistors on the same substrate using low-temperature gate dielectric treatments

A method of fabricating an integrated circuit (IC), the method comprising:

• performing fabrication operations to form an extended-gate field effect transistor (EG-FET) and a standard-gate field effect transistor (SG-FET) on a substrate, wherein the EG-FET provides a maximum extended gate (EG) threshold voltage, wherein the SG-FET provides a maximum standard gate (SG) threshold voltage that is less than the maximum EG threshold voltage, and wherein the fabrication operations include:
• forming a stack in an SG region of the substrate, wherein the stack comprises a layer of a first type of semiconductor material, a layer of a second type of semiconductor material, and an interface between the layer of the first type of semiconductor material and the layer of the second type of semiconductor material;
• depositing an SG gate dielectric over the stack;
• forming a channel in an EG region of the substrate;
• depositing a first EG gate dielectric over the channel at a first low-temperature;
• wherein the first EG gate dielectric comprises a first quality level, the first quality level being defined by a measurable property of the EG gate dielectric that is correlated with an ability of the EG-FET to provide the maximum EG threshold voltage;
• applying a reinforcement treatment to the first EG gate dielectric at a second low-temperature, wherein the reinforcement treatment converts the first EG gate dielectric to a reinforced first EG gate dielectric comprising a second quality level, the second quality level being defined by the measurable property and being correlated with an increased ability of the EG-FET to provide the maximum EG threshold voltage relative to the first quality level;
• wherein the second quality level is greater than the first quality level.