SiC MOSFETs with saturation current pinching structures

An integrated circuit comprising a SiC MOSFET and a SiC SBR (super barrier rectifier) disposed in one unit cell having an asymmetric planar gate electrode structure comprising:

• an epitaxial layer of a first conductivity type comprising multiple sub-epitaxial layers grown on a substrate;
• said asymmetric planar gate electrode structure formed in said epitaxial layer has a first gate electrode isolated from said epitaxial layer with a first gate oxide of said SiC MOSFET, and a second gate electrode isolated from said epitaxial layer with a second gate oxide of said SiC SBR, wherein said second gate oxide has a thickness less than a thickness of said first gate oxide;
• a source region of said first conductivity type encompassed in a first body region of said second conductivity type at one side of a top portion of said epitaxial layer in said SiC MOSFET and encompassed in a second body region of said second conductivity at the other side in said SiC SBR;
• a first channel region formed between said first body region and said source region;
• a second channel region formed between said second body region and said source region;
• wherein said second channel region has a channel length shallower than a channel length of said first channel region;
• said source region and said second body region of said SiC SBR shorted together with said second gate electrode to a source metal through a source contact and a gate contact of said SiC SBR;
• said integrated circuit further comprising:
• a SJ structure generated by said epitaxial layer with a PC region of said second conductivity type disposed above said substrate and connecting to said body region;
• a first type first type Junction Field Effect Transistor (JFET) region of said first conductivity type formed between two adjacent said body regions;
• an ND region of said first conductivity type formed between said substrate and said first type JFET region;
• at least two BPS regions of said second conductivity type facing each other with a doping concentration higher than a doping concentration of said PC region, adjoining said PC region and spaced apart from said body region;
• a second type JFET regions of said first conductivity type formed between said two BPS regions;
• at least one saturation current pinching (SCP) region disposed between two said adjacent PC regions comprising said second type JFET and said two BPS regions;
• an enhanced conductivity modulation (ECM) region of said first conductivity type formed in said ND region between said first type JFET and said second type JFET region with a doping concentration not less than doping concentrations of said sub-epitaxial layers below said ECM region;
• and
• said source region, said first and second body regions shorted together to said source metal.

A SiC device comprising a plurality of unit cells with each unit cell in an active area, comprising:

• an epitaxial layer of a first conductivity type comprising multiple sub-epitaxial layers grown on a substrate;
• a gate trench formed in said epitaxial layer, and surrounded by a source region of said first conductivity type encompassed in a body region of a second conductivity type at a top portion of said epitaxial layer;
• said gate trench being filled with a gate electrode, and insulated from said epitaxial layer by a first insulating film on a bottom of said gate trench, and being insulated from said epitaxial layer along sidewalls by a gate oxide;
• said first insulating film is thicker than said gate oxide;
• a source region of said first conductivity type formed at a top portion of said epitaxial layer and encompassed in a body region of said second conductivity type;
• a SJ structure generated by said epitaxial layer with a PC region of said second conductivity type disposed above said substrate and connecting to said body region;
• an ND region of said first conductivity type formed between said substrate and said bottom of said gate trench;
• at least two BPS regions of said second conductivity type facing each other with a doping concentration higher than a doping concentration of said PC region, adjoining said PC region and spaced apart from said body region;
• a JFET region of said first conductivity type formed between said two BPS regions;
• a P+ shielding region of said second conductivity type sandwiched between said body region and said PC region;
• at least one saturation current pitching (SCP) region disposed between said two adjacent PC regions comprising a JFET region and said two BPS regions;
• an enhanced conductivity modulation (ECM) region of said first conductivity type formed in said ND region between said JFET region and said bottom of said gate trench with a doping concentration equal to or higher than doping concentrations of said sub-epitaxial layers below said ECM region;
• and
• said source and body regions shorted together to a source metal.