Electronic device with galvanic isolation and integration methods
AssigneeGlobalfoundries Singapore Pte. Ltd.
InventorsBong Woong Mun, Juan Boon Tan, Szu Huat Goh, Jeoung Mo Koo
Life of this patent
Estimating the term…
Abstract
An electronic device is provided, the device comprising an interposer including a dielectric material and an interconnect structure. An integrated circuit chip may be arranged over the interposer. A galvanic capacitor may be spaced from the integrated circuit chip. The galvanic capacitor having a first electrode and a second electrode. The first electrode of the galvanic capacitor may be coupled to the integrated circuit chip. A molding material may be arranged over the integrated circuit chip and the galvanic capacitor, whereby the integrated circuit chip may be spaced from the galvanic capacitor by at least a portion of the molding material.
Claims17
An electronic device comprising:
- an interposer including a dielectric material and an interconnect structure;
- an integrated circuit chip over the interposer;
- a galvanic capacitor spaced from the integrated circuit chip, the galvanic capacitor having a first electrode and a second electrode, and the first electrode of the galvanic capacitor is coupled to the integrated circuit chip;
- and
- a molding material over the integrated circuit chip and the galvanic capacitor, wherein the integrated circuit chip is spaced from the galvanic capacitor by at least a portion of the molding material,
- wherein the first electrode of the galvanic capacitor is a first conductive plate and the second electrode of the galvanic capacitor is a second conductive plate arranged below the first conductive plate and at least partially underlapping the first conductive plate, the first conductive plate is arranged over and external to the interposer, and the second conductive plate is disposed in the interposer, wherein the first conductive plate is in a second chip laterally adjacent to the integrated circuit chip, and the second conductive plate in the interposer directly contacts the second chip.
An electronic device comprising:
- an interposer including a dielectric material and an interconnect structure;
- an integrated circuit chip over the interposer;
- a galvanic capacitor laterally spaced from the integrated circuit chip, the galvanic capacitor having a first electrode and a second electrode, and the first electrode of the galvanic capacitor is electrically coupled to the integrated circuit chip;
- and
- a molding material over the integrated circuit chip and the galvanic capacitor, wherein the integrated circuit chip is spaced from the galvanic capacitor by at least a portion of the molding material,
- wherein the first electrode of the galvanic capacitor is a first conductive plate and the second electrode of the galvanic capacitor is a second conductive plate arranged below the first conductive plate and at least partially underlapping the first conductive plate, the first conductive plate is arranged over and external to the interposer, and the second conductive plate is disposed in the interposer, wherein the first conductive plate is in a second chip on the interposer and laterally adjacent to the integrated circuit chip, and the second conductive plate in the interposer directly contacts the second chip.
A method of fabricating an electronic device comprising:
- forming a molding material over an integrated circuit chip;
- forming a galvanic capacitor, the galvanic capacitor having a first electrode and a second electrode, the first electrode of the galvanic capacitor is coupled to the integrated circuit chip, and the galvanic capacitor is spaced from the integrated circuit chip by at least a portion of the molding material;
- and
- forming an interposer including a dielectric material and an interconnect structure, wherein the interposer is below the integrated circuit chip,
- wherein the first electrode of the galvanic capacitor is a first conductive plate and the second electrode of the galvanic capacitor is a second conductive plate formed below the first conductive plate and at least partially underlapping the first conductive plate, the first conductive plate is formed over and external to the interposer, and the second conductive plate is formed in the interposer, wherein the first conductive plate is formed in a second chip, the second chip is disposed laterally adjacent to the integrated circuit chip, and the second conductive plate in the interposer directly contacts the second chip.
Dependencies are inferred from the claim text.