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US 12,676,617 B2Granted
Deterministic jitter compensation scheme for DTC timing path
AssigneeTexas Instruments Incorporated
InventorsYogesh Darwhekar, Abhrarup Barman Roy, Subhashish Mukherjee, Peeyoosh Mirajkar
Life of this patent
Estimating the term…
Abstract
In an example, a system includes an N divider coupled to an output of a low dropout regulator. The system also includes a load balancing circuit coupled to the N divider and configured to sink a load balancing current at the output of the low dropout regulator during one or more phases of the N divider. The system includes a switch coupled to the load balancing circuit and configured to connect the load balancing circuit to the output of the low dropout regulator during the one or more phases of the N divider.
Claims20
A fractional output divider (FOD), comprising:
- a transistor having first and second terminals and a control terminal, the first terminal of the transistor coupled to a supply voltage terminal;
- a frequency divider circuit having a first terminal coupled to the second terminal of the transistor, and having a second terminal, the frequency divider circuit configured to apply a first frequency divider value to an input signal in a first time period and apply a second frequency divider value to the input signal in a second time period, wherein the first frequency divider value is a first integer, and the second frequency divider value is a second integer and is greater than the first frequency divider value;
- a load balancer having a first terminal, and having a second terminal coupled to the second terminal of the frequency divider circuit, the load balancer configured to provide a current;
- a switch having a first terminal coupled to the second terminal of the transistor and having a second terminal coupled to the first terminal of the load balancer;
- a controller configured to close the switch in the second time period and to open the switch in the first time period;
- and
- a low dropout regulator having an output coupled to the control terminal of the transistor and having an input coupled to the second terminal of the transistor.
4 more elements
A system, comprising:
- a frequency divider circuit configured to divide a frequency of an input signal by an integer N in a first time period and divide the frequency of the input signal by an integer N+1 in a second time period, the frequency divider circuit having first and second terminals;
- a load balancer having a first terminal, and having a second terminal coupled to the second terminal of the frequency divider circuit, the load balancer configured to provide a current;
- a switch having a first terminal, and having a second terminal coupled to the first terminal of the load balancer;
- a low dropout regulator having an output, having a reference input, and having a second input;
- a transistor having a control terminal coupled to the output of the low dropout regulator, having a first terminal coupled to a supply voltage terminal, and having a second terminal coupled to the second input of the low dropout regulator, to the first terminal of the frequency divider circuit, and to the second terminal of the transistor;
- and
- a controller configured to close the switch in the second time period and to open the switch in the first time period.
4 more elements
A system, comprising:
- a pass transistor having a control terminal, a first terminal, and a second terminal;
- a low dropout regulator having a reference input, a second input, and an output, the second input coupled to the second terminal of the pass transistor, the output coupled to the control terminal of the pass transistor;
- a frequency divider circuit having a first terminal coupled to the second terminal of the pass transistor, and having a second terminal, the frequency divider circuit configured to apply a first frequency divider value to an input signal in a first time period and apply a second frequency divider value to the input signal in a second time period, wherein the second frequency divider value is greater than the first frequency divider value;
- a sense transistor having a control terminal coupled to the output of the low dropout regulator, having a first terminal coupled to the first terminal of the pass transistor, and having a second terminal coupled to a test terminal;
- a switch having a first terminal coupled to the second terminal of the pass transistor, to the second input of the low dropout regulator, and to the first terminal of the frequency divider circuit, and having a second terminal;
- a load balancer having a first terminal coupled to the second terminal of the switch, and having a second terminal coupled to the second terminal of the frequency divider circuit, the load balancer configured to provide a current;
- and
- a controller configured to open the switch throughout the first time period and to close the switch a portion of the second time period, and configured to set a magnitude of the current during the portion of the second time period.
5 more elements
Dependencies are inferred from the claim text.