High speed dynamic compartor

A dynamic comparator, comprising:

• an amplifier circuit comprising:
• a first differential input and a second differential input;
• a first differential amplifier output and a second differential amplifier output;
• and
• a clock input configured to receive a clock signal with a first state corresponding to an inactive phase of the dynamic comparator and a second state corresponding to an active phase of the dynamic comparator, the amplifier circuit configured to be inactive during the first state of the clock signal and configured to amplify a difference between the first differential input and the second differential input during the second state of the clock signal;
• a latch circuit comprising:
• a first transistor having a gate coupled to the first differential amplifier output, the first transistor configured to drive a first leg of the latch circuit with a first drive current;
• and
• a second transistor having a gate coupled to the second differential amplifier output, the second transistor configured to drive a second leg of the latch circuit with a second drive current;
• and
• wherein the first leg and the second leg are configured to latch a first differential output and a second differential output of the latch circuit during the active phase of the dynamic comparator in response to the first and second differential amplifier outputs;
• and
• a boost circuit comprising:
• a first boost transistor having a gate coupled to the first differential amplifier output and a source coupled to a source of the first transistor, the first boost transistor configured to provide a first supplemental current to the first differential output of the latch circuit to supplement the first drive current during the active phase;
• a first pass transistor coupled in series with the first boost transistor and configured to block the first supplemental current in response to the latch circuit latching;
• a second boost transistor having a gate coupled to the second differential amplifier output and a source coupled to a source of the second transistor, the second boost transistor configured to provide a second supplemental current to the second differential output of the latch circuit to supplement the second drive current during the active phase;
• and
• a second pass transistor coupled in series with the second boost transistor and configured to block the second supplemental current in response to the latch circuit latching.

A method for performing a dynamic comparison of a comparator, comprising:

• amplifying a difference between a first differential input and a second differential input to generate a first differential amplifier output and a second differential amplifier output;
• driving a gate of a first transistor included in a first leg of a latch circuit with the first differential amplifier output;
• driving a gate of a second transistor included in a second leg of the latch circuit with the second differential amplifier output;
• providing a first supplemental current to a first differential output of the latch circuit with a first boost transistor having a gate coupled to the first differential amplifier output and a source coupled to a source of the first transistor, the first supplemental current supplementing a first drive current provided to the first leg by the first transistor;
• providing a second supplemental current to a second differential output of the latch circuit with a second boost transistor having a gate coupled to the second differential amplifier output and a source coupled to a source of the second transistor, the second supplemental current supplementing a second drive current provided to the second leg by the second transistor;
• latching the first and second differential outputs of the latch circuit based on the first and second differential amplifier outputs;
• detecting whether the first and second differential outputs of the latch circuit have been latched during an active phase of the comparator;
• and
• blocking the first supplemental current and the second supplemental current in response to detecting that the first and second differential outputs of the latch circuit have been latched.