Level shifter

A level shifter, comprising:

• an inverter, configured to invert an input voltage of the level shifter to generate an inverted input voltage based on a first reference voltage;
• a first N-type transistor, wherein a gate terminal of the first N-type transistor is configured to receive the input voltage, and a source terminal of the first N-type transistor is coupled to a third reference voltage;
• a second N-type transistor, wherein a gate terminal of the second N-type transistor is configured to receive the inverted input voltage, and a source terminal of the second N-type transistor is coupled to the third reference voltage;
• a third N-type transistor, wherein a source terminal of the third N-type transistor is coupled to a drain terminal of the first N-type transistor, and a gate terminal of the third N-type transistor is configured to receive a bias voltage;
• a fourth N-type transistor, wherein a source terminal of the fourth N-type transistor is coupled to a drain terminal of the second N-type transistor, and a gate terminal of the fourth N-type transistor is configured to receive the bias voltage;
• a first P-type transistor, wherein a gate terminal of the first P-type transistor is coupled to the drain terminal of the second N-type transistor, a drain terminal of the first P-type transistor is coupled to a drain terminal of the third N-type transistor, and a source terminal of the first P-type transistor is configured to receive a second reference voltage;
• a second P-type transistor, wherein a gate terminal of the second P-type transistor is coupled to the drain terminal of the first N-type transistor, a drain terminal of the second P-type transistor is coupled to a drain terminal of the fourth N-type transistor, and a source terminal of the second P-type transistor is configured to receive the second reference voltage;
• a fifth P-type transistor, wherein a gate terminal of the fifth P-type transistor is coupled to a drain terminal of the fifth P-type transistor, and a source terminal of the fifth P-type transistor is configured to receive the second reference voltage;
• at least one sixth P-type transistor, coupled between the drain terminal of the fifth P-type transistor and the drain terminal of the first N-type transistor;
• and
• at least one seventh P-type transistor, coupled between the drain terminal of the fifth P-type transistor and the drain terminal of the second N-type transistor;
• wherein a gate terminal of the at least one sixth P-type transistor is coupled to the drain terminal of the second N-type transistor, and a gate terminal of the at least one seventh P-type transistor is coupled to the drain terminal of the first N-type transistor;
• wherein the level shifter generates an output voltage according to either a first shifted voltage on the drain terminal of the third N-type transistor or a second shifted voltage on the drain terminal of the fourth N-type transistor.