US 12,676,170 B2 · Bitline sense amplifiers and semiconductor devices including the same

Abstract

A bitline sense amplifier comprising: a P-type sense amplifier including a first PMOS transistor and a second PMOS transistor, wherein the first PMOS transistor and the second PMOS transistor are electrically connected to a first sense enable line; an N-type sense amplifier including a first NMOS transistor and a second NMOS transistor, wherein the first NMOS transistor and the second NMOS transistor are electrically connected to a second sense enable line; a first isolation transistor electrically connected to the first PMOS transistor and to the first NMOS transistor; a second isolation transistor electrically connected to the second PMOS transistor and to the second NMOS transistor; a first transistor electrically connected to a first node that is between the first PMOS transistor and the first isolation transistor; and a second transistor electrically connected to a second node that is between the second PMOS transistor and the second isolation transistor.

Claims20

Dependent claims

A bitline sense amplifier comprising:

a P-type sense amplifier including a first p-channel metal-oxide-semiconductor (PMOS) transistor and a second PMOS transistor, wherein the first PMOS transistor and the second PMOS transistor are electrically connected to a first sense enable line;
an N-type sense amplifier including a first n-channel metal-oxide-semiconductor (NMOS) transistor and a second NMOS transistor, wherein the first NMOS transistor and the second NMOS transistor are electrically connected to a second sense enable line;
a first isolation transistor electrically connected to the first PMOS transistor and to the first NMOS transistor;
a second isolation transistor electrically connected to the second PMOS transistor and to the second NMOS transistor;
a first transistor electrically connected to a first node that is between the first PMOS transistor and the first isolation transistor;
and
a second transistor electrically connected to a second node that is between the second PMOS transistor and the second isolation transistor.

4 more elements

A semiconductor device comprising:

a P-type sense amplifier and an N-type sense amplifier, wherein the P-type sense amplifier and the N-type sense amplifier are electrically connected to a bitline and a complementary bitline;
a first isolation transistor and a second isolation transistor that are electrically connected to the P-type sense amplifier and to the N-type sense amplifier;
a first transistor electrically connected to a first node that is between the first isolation transistor and the P-type sense amplifier;
a second transistor electrically connected to a second node that is between the second isolation transistor and the P-type sense amplifier;
and
a control logic configured to control on-off switching of each of the first isolation transistor, the second isolation transistor, the first transistor, and the second transistor, and configured to control a voltage of a first sense enable line electrically connected to the P-type sense amplifier and a voltage of a second sense enable line electrically connected to the N-type sense amplifier,
wherein the control logic is further configured to turn on the first transistor and the second transistor and turn off the first isolation transistor and the second isolation transistor in a first offset canceling operation, turn off the first transistor and the second transistor and input a first power voltage to each of the first sense enable line and the second sense enable line in a second offset canceling operation, and turn on the first transistor and the second transistor in a third offset canceling operation.

4 more elements

A semiconductor device comprising:

a bitline sense amplifier electrically connected to a bitline, a complementary bitline, a first sense enable line, and a second sense enable line;
and
a control logic configured to control the bitline sense amplifier to execute a read operation to read data from a memory cell electrically connected to the bitline,
wherein the bitline sense amplifier includes a P-type sense amplifier electrically connected to the first sense enable line, an N-type sense amplifier electrically connected to the second sense enable line, an isolation circuit electrically connected to the P-type sense amplifier and to the N-type sense amplifier, and an offset canceling circuit electrically connected to nodes that are between the P-type sense amplifier and the isolation circuit,
wherein the control logic is further configured to electrically connect the nodes to each other through the offset canceling circuit to compensate for an offset of the N-type sense amplifier and an offset of the P-type sense amplifier, while isolating the P-type sense amplifier and the N-type sense amplifier and applying a first power supply voltage to the second sense enable line, and
wherein the bitline sense amplifier includes transistors that are symmetrically positioned.

3 more elements

Dependencies are inferred from the claim text.

Bitline sense amplifiers and semiconductor devices including the same

Life of this patent

Bitline sense amplifiers and semiconductor devices including the same

Life of this patent

Abstract

Claims20