Unified memory for integrated circuit executing neural network

An integrated circuit (IC) comprising:

• a microprocessor circuit for loading configuration for a neural network and generating instructions for executing the neural network based on the configuration;
• a neural network inference circuit for executing the neural network for input data according to the instructions received from the microprocessor circuit, the neural network inference circuit comprising a plurality of cores;
• an input processing circuit for receiving data and preparing the input data for the neural network inference circuit;
• a unified memory accessible by the microprocessor circuit, the neural network inference circuit, and the input processing circuit, wherein the unified memory comprises a plurality of memory banks, and wherein a first core of the plurality of cores of the neural network inference circuit is configured to have exclusive access from among the plurality of cores to only a respective first subset of dedicated memory banks of the plurality of memory banks, and wherein a second core of the plurality of cores of the neural network inference circuit is configured to have exclusive access from among the plurality of cores to only a second subset of dedicated memory banks of the plurality of memory banks;
• and
• at least a first direct connection from the first core of the plurality of cores to a first dedicated memory bank of a first subset of dedicated memory banks,
• wherein the input processing circuit writes first input data to the first subset of dedicated memory banks and second input data to the second subset of dedicated memory banks, and
• wherein a logical address of the first subset of dedicated memory banks is swapped with a logical address of the second subset of dedicated memory banks, after executing, by the neural network inference circuit, the first input data.