Hybrid network-on-chip (NoC) for thread synchronization in many-core neural network accelerators
AssigneeMoffett International Co., Limited
InventorsZhibin Xiao, Xiaoqian Zhang
Life of this patent
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Abstract
This application describes a network-on-chip system that could be used in a hardware accelerator for accelerating neural network computations. An example NoC system may include a plurality of cores, and a plurality of data links connecting adjacent cores of the plurality of cores for transmitting data. The example NoC may further include a global synchronization switch connected to each of the plurality of cores. The global synchronization switch is configured to dynamically connect any pair of cores in the plurality of cores for transmitting control signals between the pair of cores.
Claims18
A Network-on-Chip (NoC), comprising:
- a plurality of cores;
- a plurality of data links connecting adjacent cores of the plurality of cores and configured to transmit data among the adjacent cores;
- and
- a global synchronization switch connected to each of the plurality of cores, wherein the global synchronization switch is configured to dynamically establish a connection between any pair of cores in the plurality of cores for transmitting control signals between the pair of cores,
- wherein the global synchronization switch comprises a core-indexed data structure having a plurality of indicators respectively corresponding to the plurality of cores, each indicator corresponding to a receiving core and is associated with a queue,
- wherein the queue stores one or more core identifiers of one or more sending cores to transmit control signals to the receiving core.
A global synchronization switch in a Network-On-Chip (NoC) comprising a plurality of cores, wherein the global synchronization switch comprises:
- a bitmap comprising a plurality of bits respectively corresponding to the plurality of cores, wherein:
- each bit in the bitmap corresponds to a core and indicates whether the core is ready to receive control signals;
- and
- each bit in the bitmap is associated with a queue, wherein the queue is configured to store one or more core identifiers associated with one or more sending cores to send control signals to the core;
- wherein the global synchronization switch is configured to:
- dynamically establish, based on the bitmap, a connection between any pair of cores in the plurality of cores, and the connection connecting the pair of cores forms a direct core-to-core transmission of control signals between the pair of cores.
A computer-implemented method implemented by a Network-On-Chip (NoC), the NoC comprising a plurality of cores, a plurality of data links connecting adjacent cores of the plurality of cores for transmitting data, and a global synchronization switch connected with each of the plurality of cores for transmitting control signals, the method comprises:
- receiving a first request from a receiving core of the plurality of cores, the first request including a status flag indicating that the receiving core is ready to receive control signals, and core identifiers of one or more sending cores of the plurality of cores to send the control signals;
- setting, in a bitmap, a bit corresponding to the receiving core and appending the core identifiers of the one or more sending cores to a queue associated with the bit;
- receiving a second request from a sending core, wherein the second request comprises a core identifier of the receiving core;
- determining, based on the core identifier of the receiving core, that the bit corresponding to the receiving core is set;
- determining that the core identifier of the sending core matches a core identifier in the queue associated with the bit;
- establishing a core-to-core connection between the sending core and the receiving core for transmitting a control signal;
- and
- transmitting data from the sending core to the receiving core using the plurality of data links.
Dependencies are inferred from the claim text.