Heterogeneous accelerator for highly efficient learning systems

A system, comprising:

• a first processing unit;
• a second processing unit;
• a third processing unit, wherein the first processing unit is configured to assign the second processing unit a first task and the third processing unit a second task;
• a High Bandwidth Memory (HBM) stack;
• and
• system memory, wherein the second processing unit is configured to write data for the first task to the system memory, and the first processing unit is further configured to initiate a triggering event indicating that the second processing unit has written data to the system memory;
• wherein the data is copied from the system memory to the HBM stack and the third processing unit processes the second task, using the data written to the HBM stack, based on the triggering event.

An apparatus, comprising:

• a first processing unit;
• a second processing unit;
• a third processing unit;
• system memory;
• and
• a High Bandwidth Memory (HBM) stack;
• wherein the second processing unit is assigned a first task and the third processing unit is assigned a second task from the first processing unit;
• wherein the second processing unit writes data for the first task to cache memory;
• wherein the second processing unit writes the data from the cache memory to the system memory;
• wherein the data is written from the system memory to the HBM stack;
• and
• wherein the second processing unit executes the second task using the data in the HBM stack based on the data being written from the system memory to the HBM stack.