Method of improving L1 icache performance with large programs
AssigneeMarvell Asia Pte Ltd
InventorsEdward McLellan, Alexander Rucker, Shay Gal-On, Srilatha Manne
Life of this patent
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Abstract
The hit rate of a L1 icache when operating with large programs is substantially improved by reserving a section of the L1 icache for regular instructions and a section for non-instruction information. Instructions are prefetched for storage in the instruction section of the L1 icache based on information in the non-instruction section of the L1 icache.
Claims22
A method of operating a computer system, the method comprising:
- accessing a L1 icache that stores regular instructions and non-instruction information, wherein the non-instruction information comprises non-sequential addresses, and wherein the non-instruction information in the L1 icache further comprises:
- an address of a read request that results in a miss in the non-instruction information in the L1 icache, and an offset corresponding to the address of the read request that is used to identify a next memory address;
- and
- prefetching the next memory address to be stored in the L1 icache, when the next memory address is not present in the L1 icache.
A computer system, comprising:
- a L1 icache that stores regular instructions and non-instruction information, wherein the non-instruction information comprises non-sequential addresses, and wherein the non-instruction information in the L1 icache further comprises:
- an address of a read request that results in a miss in the non-instruction information in the L1 icache, and an offset corresponding to the address of the read request that is used to identify a next memory address;
- and
- a processor coupled to the L1 icache, the processor being configured to prefetch the next memory address to be stored in the non-instruction information in the L1 icache, when the next memory address is not present in the non-instruction information in the L1 icache.
A non-transitory computer-readable medium having computer-readable instructions stored thereon which, when executed by a processor, cause the processor to execute a method of cache prefetching, the method comprising:
- accessing a L1 icache that stores regular instructions and non-instruction information, wherein the non-instruction information comprises non-sequential addresses, and wherein the non-instruction information in the L1 icache further comprises:
- an address of a read request that results in a miss in the non-instruction information in the L1 icache, and an offset corresponding to the address of the read request that is used to identify a next memory address;
- and
- prefetching the next memory address to be stored in the non-instruction information in the L1 icache, when the next memory address is not present in the non-instruction information in the L1 icache.
Dependencies are inferred from the claim text.