Cycle accurate tracing of vector instructions

A method comprising:

• capturing a plurality of bits at checkpoints implemented in a vector unit in communication with a scalar core, the vector unit including a vector instruction queue that receives vector instructions from the scalar core, the vector unit further including a vector execution unit that executes vector instructions from the vector instruction queue, wherein the checkpoints include a first checkpoint including first hardware circuitry that sets a first bit for a first clock cycle in which a first vector instruction exits the vector instruction queue, and a second checkpoint including second hardware circuitry that is separate from the first hardware circuitry and that sets a second bit for a second clock cycle in which a second vector instruction exits the vector execution unit;
• and
• executing a trace encoder to associate a vector instruction obtained from the scalar core with a bit obtained from a checkpoint.

A non-transitory computer-readable storage medium that includes instructions that, when executed by a processor, causes the processor to:

• associate a vector instruction obtained from a scalar core with a bit obtained from a checkpoint of a plurality of checkpoints implemented in a vector unit in communication with the scalar core, wherein the vector unit includes a vector instruction queue that receives vector instructions from the scalar core, wherein the vector unit further includes a vector execution unit that executes vector instructions from the vector instruction queue, and wherein the plurality of checkpoints includes a first checkpoint including first hardware circuitry that sets a first bit for a first clock cycle in which a first vector instruction exits the vector instruction queue, and a second checkpoint including second hardware circuitry that is separate from the first hardware circuitry and that sets a second bit for a second clock cycle in which a second vector instruction exits the vector execution unit;
• and
• display a trace of the vector instruction, wherein the trace indicates a number of clock cycles between the first checkpoint and the second checkpoint.