Debug and recovery operations for non-removable memory sub-systems
AssigneeMicron Technology, Inc.
InventorsNicholas Terence Heath, Gaurav Sinha
Life of this patent
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Abstract
A processing device in a host system detecting a failure of a memory sub-system coupled to the host system and collects debug information from the memory sub-system via a memory sub-system interface. Responsive to determining that the debug information is not sufficient to correct the failure of the memory sub-system, the processing device performing an authentication process to authenticate the system to the memory sub-system, collects enhanced debug information from the memory sub-system via the memory sub-system interface, and performs one or more corrective actions based on the enhanced debug information to correct the failure of the memory sub-system.
Claims20
A system comprising:
- a memory sub-system interface;
- and
- a processing device, operatively coupled with the memory sub-system interface, to perform operations comprising:
- detecting a failure of a memory sub-system coupled to the memory sub-system interface;
- collecting debug information from the memory sub-system via the memory sub-system interface;
- determining whether the debug information is sufficient to correct the failure of the memory sub-system;
- and
- responsive to determining that the debug information is not sufficient to correct the failure of the memory sub-system:
- performing an authentication process to authenticate the system to the memory sub-system;
- and
- collecting enhanced debug information from the memory sub-system via the memory sub-system interface.
A method comprising:
- detecting a failure of a memory sub-system coupled to a host system via a memory sub-system interface;
- collecting debug information from the memory sub-system via the memory sub-system interface;
- determining whether the debug information is sufficient to correct the failure of the memory sub-system;
- and
- responsive to determining that the debug information is not sufficient to correct the failure of the memory sub-system:
- performing an authentication process to authenticate the host system to the memory sub-system;
- and
- collecting enhanced debug information from the memory sub-system via the memory sub-system interface.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
- detecting a failure of a memory sub-system coupled to a host system via a memory sub-system interface;
- collecting debug information from the memory sub-system via the memory sub-system interface;
- determining whether the debug information is sufficient to correct the failure of the memory sub-system;
- and
- responsive to determining that the debug information is not sufficient to correct the failure of the memory sub-system:
- performing an authentication process to authenticate the host system to the memory sub-system;
- collecting enhanced debug information from the memory sub-system via the memory sub-system interface;
- and
- performing one or more corrective actions based on the enhanced debug information to correct the failure of the memory sub-system.
Dependencies are inferred from the claim text.