System and method for distributed forwarding logic for cyclic data-pipeline coherency

A computing system comprising:

• a memory;
• and
• a computing device operatively coupled to the memory, the computing device configured to:
• process data using a plurality of stages of a data processing pipeline;
• identify, based on a comparison of an input and an output of each stage of the plurality of stages, a data modification stage in the plurality of stages;
• forward modified data from the data modification stage to each of the other stages of the plurality of stages, wherein each stage of the plurality of stages comprises selection logic to select between output data from a previous stage or the modified data from the data modification stage as input to an operator of the corresponding stage and wherein the modified data is provided as an input to the selection logic at each of the other stages;
• at each respective stage in the plurality of stages, compare an address of output data received from the previous stage relative to the respective stage with an address of the modified data;
• in response to determining that the address of the output data from the previous stage is the same as the address of the modified data, select, using the selection logic, the modified data for processing in the respective stage;
• and
• process the modified data in the respective stage of the data processing pipeline.

A non-transitory computer readable medium having instructions stored thereon which, when executed by a processor, cause the processor to:

• process data using a plurality of stages of a data processing pipeline executed using a Field Programmable Gate Array (FPGA);
• identify, based on a comparison of an input and an output of each stage of the plurality of stages, a data modification stage in the plurality of stages;
• forward modified data from the data modification stage to each of the other stages of the plurality of stages, wherein each stage of the plurality of stages comprises selection logic to select between output data from a previous stage or the modified data from the data modification stage as input to an operator of the corresponding stage and wherein the modified data is provided as an input to the selection logic at each of the other stages;
• at each respective stage in the plurality of stages, compare an address of output data received from the previous stage relative to the respective stage with an address of the modified data;
• in response to determining that the address of the output data from the previous stage is the same as the address of the modified data, select, using the selection logic, the modified data for processing in the respective stage;
• and
• process the modified data in the respective stage of the data processing pipeline.