US 12,675,018 B2Granted

Variable pitch fan-out routing for display panels having narrow borders

AssigneeParade Technologies, Ltd.

InventorsYou Ben Yin, Quan Yu, Yueh-Lin Yang

Life of this patent

Estimating the term…

Loading patent…

Abstract

An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area is divided to a plurality of fan-out regions, and has interconnects configured to access display elements formed on the display area. The driver area is adjacent to the fan-out area and configured to receive a driver chip having a plurality of pads. The interconnects of the fan-out area include a subset of first interconnects. Each first interconnect passes a first fan-out region and a second fan-out region to access a respective display element. A first portion of the subset of first interconnects is formed on the first fan-out region with a first interconnect pitch, and a second portion of the subset of first interconnects is formed on the second fan-out region with a second interconnect pitch different from the first interconnect pitch.

Claims20

Dependent claims

An electronic device, comprising:

a display substrate;
a display area formed on the display substrate and having a plurality of display elements;
and
a fan-out area located adjacent to the display area on the display substrate and having a plurality of interconnects, wherein the fan-out area is divided to a plurality of fan-out regions;
wherein the plurality of interconnects include a subset of first interconnects, and each first interconnect passes a first fan-out region and a second fan-out region to access the display area, the first fan-out region having a region width equal to or greater than a driver width of a driver chip, the second fan-out region being external to the first fan-out region;
and
wherein a first portion of the subset of first interconnects is formed on the first fan-out region with a first interconnect pitch, and a second portion of the subset of first interconnects is formed on the second fan-out region with a second interconnect pitch, the second interconnect pitch different from the first interconnect pitch.

4 more elements

An apparatus, comprising:

a display substrate;
a display area formed on the display substrate and having a plurality of display elements;
and
a fan-out area located adjacent to the display area on the display substrate and having a plurality of interconnects, wherein the fan-out area is divided to a plurality of fan-out regions;
wherein the plurality of interconnects include a subset of first interconnects, and each first interconnect passes a first fan-out region and a second fan-out region to access the display area, the first fan-out region having a region width equal to or greater than a driver width of a driver chip, the second fan-out region being external to the first fan-out region;
and
wherein a first portion of the subset of first interconnects is formed on the first fan-out region with a first interconnect pitch, and a second portion of the subset of first interconnects is formed on the second fan-out region with a second interconnect pitch, the second interconnect pitch different from the first interconnect pitch.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/032,952Filed 21 Jan 2025 · continuation
Priority: CN 202211238303.810 Oct 2022
Published: US 2025/0172841 A129 May 2025
Granted: 7 Jul 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G02F 1/13452
Conductors connecting electrodes to cell terminals: conductors connecting driver circuitry and terminals of panels
G02F 1/13338
Constructional arrangements; Manufacturing methods: input devices, e.g. touch panels
G02F 1/13458
Conductors connecting electrodes to cell terminals: terminal pads
G06F 3/0412
Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means: digitisers structurally integrated in a display

Family

Application17/334,370Parent of this continuation-in-part · filed 28 May 2021
Application17/488,263Parent of this continuation-in-part · filed 28 Sep 2021
Application17/974,407Parent of this continuation-in-part · filed 26 Oct 2022
US 11,592,715 B2Parent of this continuation-in-part · filed 28 Feb 2023
Application18/182,268Parent of this continuation · filed 10 Mar 2023
US 11,676,974 B2Parent of this continuation-in-part · filed 13 Jun 2023
US 2025/0172841 A1Pre-grant publication · published 29 May 2025
US 12,222,611 B2Parent of this continuation
Application18/182,268Parent of this continuation-in-part
US 12,560,844 B2Related patent
US 2022/0382094 A1Published application
US 2022/0384489 A1Published application
US 2023/0045931 A1Published application
US 2023/0229044 A1Published application
US 12,675,018 B2This patent

From the US filing history. Foreign family members aren’t listed.