Wireless circuitry with low-noise peak detection

Wireless circuitry comprising:

• a radio-frequency transmission line path configured to convey a radio-frequency signal;
• an analog-to-digital converter (ADC);
• a peak detector having an output communicatively coupled to the ADC, wherein the peak detector includes
• a differential pair of transistors coupled between a power supply voltage and the output,
• a first transistor having a first gate terminal configured to receive the radio-frequency signal from the radio-frequency transmission line path and having a first source-drain terminal coupled to the output, and
• a second transistor having a second source-drain terminal coupled to the output and the first source-drain terminal, having a second gate terminal coupled to the second source-drain terminal, and having a third source-drain terminal coupled to the first gate terminal;
• a third transistor having a third gate terminal and having a fourth source-drain terminal, the fourth source-drain terminal being coupled to the output;
• a fourth transistor having a fifth source-drain terminal coupled to the output and the fourth source-drain terminal, having a fourth gate terminal coupled to the fifth source-drain terminal, and having a sixth source-drain terminal coupled to the third gate terminal;
• and
• a fifth transistor having a seventh source-drain terminal communicatively coupled to the first gate terminal and the third gate terminal and having a fifth gate terminal coupled to the seventh source-drain terminal.

A voltage peak detector having an input terminal and a differential output, the voltage peak detector comprising:

• a first transistor having a first gate terminal communicatively coupled to the input terminal, having a first source-drain terminal coupled to a first output terminal of the differential output, and having a second source-drain terminal communicatively coupled to a ground;
• a second transistor having a third source-drain terminal coupled to a power supply voltage and having a fourth source-drain terminal coupled to the first output terminal;
• a diode-connected transistor having a fifth source-drain terminal coupled to the first output terminal and having a sixth source-drain terminal coupled to the first gate terminal;
• and
• a third transistor, wherein the third transistor has a seventh source-drain terminal communicatively coupled to the first gate terminal and the sixth source-drain terminal;
• and
• a fourth transistor having a second gate terminal, an eighth source-drain terminal coupled to a second output terminal of the differential output, and a ninth source-drain terminal communicatively coupled to the ground, wherein the seventh source-drain terminal is communicatively coupled to the second gate terminal.