Low temperature hybrid bonding metallization
AssigneeApplied Materials, Inc.
InventorsJing Xu, John Klocke
Life of this patent
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Abstract
A semiconductor wafer, including a substrate, at least one via formed in the substrate, and copper electroplating inside the at least one via, where the copper electroplating comprises a first layer of nanotwin copper, and a second layer of bulk copper. Further, a method of making a semiconductor wafer, the method comprising providing a substrate; etching the substrate to form at least one via; and depositing copper electroplating inside the at least one via, wherein the copper electroplating comprises a first layer of nanotwin copper, and a second layer of bulk copper.
Claims17
A semiconductor wafer, comprising:
- a substrate;
- at least one via formed in the substrate;
- and
- a copper electroplating inside the at least one via, wherein the copper electroplating comprises a first layer of nanotwin copper, and a second layer of bulk copper, wherein the bulk copper is fine grain copper.
A method of making a semiconductor wafer, the method comprising:
- providing a substrate;
- etching the substrate to form at least one via;
- depositing a first layer of nanotwin copper inside the at least one via;
- and
- depositing a second layer of bulk copper inside the at least one via, wherein the second layer of bulk copper is a fine grain copper.
Dependencies are inferred from the claim text.