US 12,672,590 B2Granted

Methods of forming microelectronic devices

AssigneeMicron Technology, Inc.

InventorsFatma Arzum Simsek-Ege, Kunal R. Parekh

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Abstract

A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, contact structures coupled to the digit lines, word lines coupled to the memory cells, additional contact structures coupled to the word lines, and isolation material surrounding the contact structures and the additional contact structures and overlying the memory cells. An additional microelectronic device structure assembly is formed and comprises control logic devices, further contact structures coupled to the control logic devices, and additional isolation material surrounding the further contact structures and overlying the control logic devices. The additional microelectronic device structure assembly is attached to the microelectronic device structure assembly by bonding the additional isolation material to the isolation material and by bonding the further contact structures to the contact structures and the additional contact structures. Microelectronic devices and electronic systems are also described.

Claims17

Dependent claims

A method of forming a microelectronic device, comprising:

forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, contact structures coupled to the digit lines, word lines coupled to the memory cells, additional contact structures coupled to the word lines, and isolation material horizontally surrounding the contact structures and the additional contact structures and vertically overlying the memory cells, the digit lines, and the word lines, wherein forming the microelectronic device structure assembly comprises:
forming a first microelectronic device structure comprising a first base semiconductor structure, the digit lines, the word lines, and access devices of the memory cells coupled to the digit lines and the word lines;
forming digit line contact structures coupled to the digit lines within digit line exit regions neighboring the access devices in a first horizontal direction;
forming word line contact structures coupled to the word lines within word line exit regions neighboring the access devices in a second horizontal direction;
forming other contact structures within socket regions;
forming storage node devices of the memory cells over and in electrical communication with the access devices of the memory cells after the forming other contact structures;
and
forming routing structures over the storage node devices of the memory cells, at least some of the routing structures coupled to at least some of the other contact structures and in electrical communication with the storage node devices;
forming an additional microelectronic device structure assembly comprising control logic devices, further contact structures coupled to the control logic devices, and additional isolation material horizontally surrounding the further contact structures and vertically overlying the control logic devices;
and
attaching the additional microelectronic device structure assembly to the microelectronic device structure assembly by bonding the additional isolation material of the additional microelectronic device structure assembly to the isolation material of the microelectronic device structure assembly and by bonding the further contact structures of the additional microelectronic device structure assembly to the contact structures and the additional contact structures of the microelectronic device structure assembly.

8 more elements

A method of forming a microelectronic device, comprising:

forming a first semiconductor wafer comprising memory cells within array regions, digit lines coupled to the memory cells and terminating within digit line exit regions neighboring the array regions, digit line contact structures extending through and in contact with the digit lines within the digit line exit regions, word lines coupled to the memory cells and terminating within word line exit regions neighboring the array regions, and word line contact structures extending through and in contact with the word lines within the word line exit regions;
forming a second semiconductor wafer comprising control logic devices, routing structures in electrical communication with the control logic devices, and contact structures horizontally offset from the control logic devices and coupled to the routing structures;
and
attaching the second semiconductor wafer to the first semiconductor wafer through a combination of oxide-oxide bonding and metal-metal bonding such that some of the control logic devices are positioned within the array regions, some of the contact structures are positioned within the digit line exit regions and are coupled to the digit line contact structures, and some other of the contact structures are positioned within the word line exit regions and are coupled to the word line contact structures.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 18/491,702Filed 20 Oct 2023 · division
Priority: 30 Jun 2021
Published: US 2024/0063205 A122 Feb 2024
Granted: 30 Jun 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10W 90/00
Package configurations
H10B 12/036
Making the capacitor or connections thereto: the capacitor extending under the transistor
H10B 12/33
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: the capacitor extending under the transistor
H10B 12/482
Data lines or contacts therefor: bit lines

Family

Application17/364,476Parent of this division · filed 30 Jun 2021
US 2024/0063205 A1Pre-grant publication · published 22 Feb 2024
US 11,837,594 B2Parent of this division
US 2023/0005903 A1Published application
US 12,672,590 B2This patent

From the US filing history. Foreign family members aren’t listed.